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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16201-3E
32-bit RISC Microcontroller
CMOS
FR20 Series MB91103
MB91103
s DESCRIPTION
The MB91103 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR20 Series) core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU processing for embedded controller applications. To support the vast memory space accessed by the 32-bit CPU, the MB91103 normally operates in the external bus access mode and executes instructions on the internal 1 KB cache memory for enhanced performance. The MB91103 is optimized for applications requiring high-performance CPU processing such as navigation systems, high-performance FAXs and printer controllers.
s FEATURES
FR20CPU * 32-bit RISC, load/store architecture, 5-stage pipeline * Operating clock frequency: 25 MHz * General purpose registers: 32-bit x 16 * 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle * Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications * Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages * Register interlock functions, efficient assembly language coding * Branch instructions with delay slots: Reduced overhead time in branch executions * Internal multiplier/Supported at instruction level Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles * Interrupt (push PC and PS): 6 cycles, 16 priority levels
(Continued)
s PACKAGE
160-pin Plastic QFP
(FPT-160P-M03)
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MB91103 Series
(Continued) Bus interface * 24-bit address bus (16 MB memory space) * 32-bit/16-bit/8-bit data bus * Basic external bus cycle: 2 clock cycles * Chip select outputs for setting down to a minimum memory block size of 64 K bytes: 6 * Interface supported for various memory technologies Time sharing input/output of data/address (area 1) DRAM interface (area 4 and 5) * Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area * Parity check function: Generates parity error interrupt * Unused data/address pins can be configured us input/output ports * Little endian mode supported (Select 1 area from area 1 to 5)
DRAM interface * 2 banks independent control (area 4 and 5) * Normal mode/high speed page mode * Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high speed page mode * Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles * DRAM refresh CBR refresh (interval time configurable by 6-bit timer) Self-refresh mode * Supports 8-bit/9-bit/10-bit/12-bit column address width * 2CAS/1WE, 2WE/1CAS selective Cache memory * 1 KB instruction cache memory * 2 way set associative * 32 blocks/way, 4 entries (4 words)/block DMAC (DMA Controller) * 5 channels * External to external 2.5 access cycle/transfer (when 2 clock cycles = 1 access cycle) * Internal to external 1.5 access cycle/transfer (when 2 clock cycles = 1 access cycle) * Address registers (inc, dec and reload executable), 32-bit x 2, 16-bit x 6 * Transfer count register ( reload executable), 16-bit x 2, 8-bit x 3 * Transfer incident/external pins/internal resource interrupt requests/software interrupts * Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer/cycle steal transfer (for ch. 0 and ch.1 only) * Transfer data length: 8-bit/6-bit/32-bit selective * Command chain operation possible * NMI/interrupt request enables temporary stop operation UART * * * * * * * * 2 2 independent channels Full-duplex double buffer Data length: 7-bit to 9-bit (non-parity), 6-bit to 8-bit (parity) Asynchronous (start-stop system), CLK-synchronized communication selective Multi-processor mode Internal 16-bit timer operating as a proprietary baud rate generator: Generates any given baud rate Use external clock can be used as a transfer clock Error detection: Parity, frame, overrun
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MB91103 Series
(Continued)
Extended I/O serial interface * Inputs/outputs 8-bit data in serial format * LSB first/MSB first selective * Shift clock internal generation/external input selective A/D converter (successive approximation type) * 10-bit resolution, 8 channels * Successive approximation type: Conversion time of 5.6 s at 25 MHz * Internal sample and hold circuit * Conversion mode: Single conversion/scanning conversion/repeated conversion selective * Start: Software/external trigger/internal timer selective Reload timer * * * * 16-bit timer: 2 channels Internal clock: 2 clock cycle resolution, divide by 2/8/32 selective Pin input: Event counter input/gate function Square wave output
Up/down counter * 16-bit timer: 2 channels * Timer mode/up/down counter mode/phase shift count mode * Pin input activates counter clear/gate function Other interval timers * 16-bit timer: 2 channels (U-TIMER), 1 channel (free run for ICU/OCU) * Watch-dog timer: 1 channel Input capture/output compare * Capture: 4 channels, compare: 8 channels * Count can be cleared on compare match * 16-bit unified free-run timer embedded Bit search module * First bit transition "1"/"0" from MSB can be detected in 1 cycle Interrupt controller * External interrupt input: Non-maskable interrupt (NMI), normal interrupt x8 (INT0 to INT7) * Internal interrupt incident: Parity error, UART, DMAC, A/D, reload timer, up/down counter, capture/compare, baud rate timer, extended serial I/O, free-run timer and delayed interrupt * Priority levels of interrupts are programmable in 16 steps (except for non-maskable interrupt) Others * Reset cause: Power-on reset/watch-dog timer/software reset/external reset * Low power consumption mode Sleep mode/stop mode * Clock gear function Operating clocks for CPU and peripherals are independently selective Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16) * Package QFP-160 * CMOS technology (0.65 m), operating voltage 5.0 V 10% 3
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MB91103 Series
s PRODUCT LINEUP
Product Items Instruction cache DMAC 1 KB fixed 5 channels (ch. 0, ch. 1, ch. 4, ch. 5 and ch. 6 only) Address register (32-bit length) x 2 (DMAAR 0, DMAAR 1) Address register (16-bit length) x 6 (DMAAR 2 to DMAAR 7) Transfer count register (16-bit length) x 2 (DMACT 0, DMACT 1) Transfer count register (8-bit length) x 3 (DMACT 4 to DMACT 6) Channels for cycle steal operation: 2 channels (ch. 0, ch. 1) 19 internal transfer causes 2 channels 2 channels MB91103 MB91V100 Max. 4 KB (4 KB/2 KB/1 KB/512 B selective) 8 channels 32-bit length x 4 (DMAAR 0 to DMAAR 3) 16-bit length x 4 (DMAAR 4 to DMAAR 7) 16-bit length x 4 (DMACT 0 to DMACT 3) 8-bit length x 4 (DMACT 4 to DMACT 7) 4 channels (ch. 0 to ch. 3) 23 internal interrupt causes
U-TIMER UART
3 channels 3 channels 12 channels (INT0 to INT11) Incorporated Incorporated
External interrupts 8 channels (INT0 to INT7) Timer units DSP unit Pin conditions in each state PG 4 to PG 7 are fixed to 0 when CPU stops
Configured as input when CPU stops
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MB91103 Series
s PIN ASSIGNMENT
(Top view)
VCC X1 X0 VSS RST OC7/PI3 OC6/PI2 OC5/PI1 OC4/PI0 OC3/PH7 VSS OC2/PH6 OC1/PH5 OC0/PH4 IC3/ZIN1/PH3 IC2/BIN1PH2 IC1/AIN1/PH1 IC0/SC2/ZIN0/PH0 TO1/BIN0/PG7 TI1/AIN0/PG6 VCC TO0PG5 TI0/PG4 DREQ1/INT7/PG3 DREQ0/PG2 DACK1/INT6/ATG/PG1 DACK0/PG0 N.C. PF7 PF6 N.C. INT5/PF5 INT4/PF4 VSS SO2/PF3 SI2/PF2 SC1/PF1 SO1/PF0 SI1/PE7 SC0/PE6 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
D00/P00 D01/P01 D02/P02 D03/P03 D04/P04 D05/P05 D06/P06 D07/P07 VSS D08/P10 D09/P11 D10/P12 D11/P13 VCC D12/P14 D13/P15 D14/P16 D15/P17 VSS D16/P20 D17/P21 D18/P22 D19/P23 VCC D20/P24 D21/P25 D22/P26 D23/P27 D24 D25 D26 D27 VSS D28 D29 D30 D31 A00 A01 A02
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
INDEX
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
SO0/PE5 SI0/PE4 INT3/PE3 INT2/PE2 INT1/PE1 INT0/PE0 VSS AN7/PD7 AN6/PD6 AN5/PD5 AN4/PD4 AVSS AVRL AVRH AVCC AN3/PD3 AN2/PD2 AN1/PD1 AN0/PD0 NMI HST MD2 MD1 MD0 DW1/PB7 DW0/PB6 CS1H/PB5 CS1L/PB4 VCC CS0H/PB3 CS0L/PB2 RAS1/PB1 RAS0/PB0 VSS CLK/PA6 CS5/PA5 CS4/PA4 CS3/PA3 CS2/PA2 CS1/PA1
Note: No connections to N.C. pins.
A03 A04 A05 A06 A07 VCC A08 A09 A10 A11 VSS A12 A13 A14 A15 A16/P60 A17/P61 A18/P62 A19/P63 A20/P64 A21/P65 A22/P66 A23/P67 RDY/P80 BGRNT/P81 BRQ/P82 RD WR0 WR1/P85 WR2/P86 WR3/P87 ACLK/P90 VSS ALE/P91 PAR0/P92 PAR1/P93 VCC PAR2/P94 PAR3/P95 CS0/PA0
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
(FPT-160P-M03)
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MB91103 Series
s PIN DESCRIPTION
Pin No. QFP* 158 159 97 to 99 X0 X1 MD0 to MD2 G Pin name Circuit type A Clock (Oscillator) input Clock (Oscillator) output Mode pins 0 to 2 Input pins for operation mode specification. Directly connect these pins with VCC or VSS for use. External reset input. Bit 0 to bit 7 of external data bus. I/O port. This function is available when external data bus width is set to 8-bit or 16-bit. J Bit 8 to bit 15 of external data bus. I/O port. This function is available when external data bus width is set to 8-bit or 16-bit. J Bit 16 to bit 23 of external data bus. I/O port. This function is available when external data bus width is set to 8-bit. J C Bit 24 to bit 31 of external data bus. Bit 0 to bit 15 of external address bus. Function
156 1 to 8
RST D00 to D07 P00 to P07
B J
10 to 13, 15 to 18
D08 to D15 P10 to P17 D16 to D23 P20 to P27 D24 to D31 A00 to A15
20 to 23, 25 to 28
29 to 32, 34 to 37 38 to 45, 47 to 50, 52 to 55 56 to 63
A16 to A23 P60 to P67
C
Bit 16 to bit 23 of external address bus. Can be configured as I/O ports when not used as address bus.
64
RDY
J
External ready input. Outputs "L" level bus cycle is being executed and not completed. Can be configured as I/O port.
P80 65 BGRNT P81 66 BRQ P82 67 68 * : FPT-160P-M03 RD WR0 C C J C
External bus release acknowledge output. Outputs "L" level when external bus is released. Can be configured as I/O port. External bus release request input. Input "H" level when release of external bus is required. Can be configured as I/O port. Read strobe output pin for external bus. Write strobe output pin for external bus.
(Continued)
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MB91103 Series
Pin No. QFP* 69 to 71
Pin name WR1 to WR3
Circuit type C
Function Write strobe output pin for external bus. Relation between control signals and effective byte locations is as follows: D31 to D24 D23 to D16 D15 to D08 D07 to D00 32-bit bus width WR0 WR1 WR2 WR3 16-bit bus width 8-bit bus width WR0 WR0 WR1 (I/O port enabled) (I/O port enabled) (I/O port enabled) (I/O port enabled) (I/O port enabled)
P85 to P87 72 74 75, 76, 78, 79 ACLK P90 ALE P91 PAR0 to PAR3 J C C
Can be configured as I/O port. Clock output for a bus cycle. Can be configured as I/O port. Address strobe signal in time-sharing mode. Can be configured as I/O port. Parity input/output. Relation between control signals and effective byte locations is as follows: D31 to D24 D23 to D16 D15 to D08 D07 to D00 32-bit bus width PAR0 PAR1 PAR2 PAR3 16-bit bus width 8-bit bus width PAR0 PAR0 PAR1 (I/O port enabled) (I/O port enabled) (I/O port enabled) (I/O port enabled) (I/O port enabled)
P92 to P95 80 to 85 86 CS0 to CS5 PA0 to PA5 CLK PA6 88 89 90 91 93 RAS0 PB0 RAS1 PB1 CS0L PB2 CS0H PB3 CS1L PB4 * : FPT-160P-M03 C C C C C C C
Can be configured as I/O port. Chip select 0 to 5 output ("L" active). Can be configured as I/O port. System clock output. Outputs clock signal of internal operating frequency. Can be configured as I/O port. RAS output for DRAM bank 0. Can be configured as I/O port. RAS output for DRAM bank 1. Can be configured as I/O port. CASL output for DRAM bank 0. Can be configured as I/O port. CASH output for DRAM bank 0. Can be configured as I/O port. CASL output for DRAM bank 1. Can be configured as I/O port.
(Continued)
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MB91103 Series
Pin No. QFP* 94 95 96 100 101 102 to 105
Pin name CS1H PB5 DW0 PB6 DW1 PB7 HST NMI AN0 to AN3
Circuit type C C C H H D
Function CASH output for DRAM bank 1. Can be configured as I/O port. WE output for DRAM bank 0. ("L" active) Can be configured as I/O port. WE output for DRAM bank 1. ("L" active) Can be configured as I/O port. Directly connects this pin with VCC for use. NMI (non-maskable interrupt pin) input pin. ("L" active) Analog input pins of A/D converter. This function is available when AIC register is set to specify analog input mode. General-purpose I/O ports. This function is available when AIC register is set to configure I/O ports.
PD0 to PD3
110 to 113
AN4 to AN7
D
Analog input pins of A/D converter. This function is available when AIC register is set to specify analog input mode. General-purpose I/O ports. This function is available when AIC register is set to configure I/O ports.
PD4 to PD7
115 to 118
INT0 to INT3
I
External interrupt request input pins. This pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. INT0 and INT1 can be used as a DMA request when DMAC is so configured. General-purpose I/O port. Data input pin for extended serial I/O interface (SIO). This pin is used for input during SIO is in operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. General-purpose I/O port. Data output for extended serial I/O interface (SIO). This function is available when serial data output specification of SIO is enabled. General-purpose I/O port. This function is available when serial data output of extended serial I/O interface (SIO) is disabled.
PE0 to PE3 119 SI0 F
PE4 120 SO0 C
PE5
121
SC0 PE6
F
Clock input/output pin for extended serial I/O interface. Clock output is valid when clock output of SIO is enabled. General-purpose I/O port. This function is available when clock output of SIO is enabled.
* : FPT-160P-M03 8
(Continued)
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MB91103 Series
Pin No. QFP* 122
Pin name SI1
Circuit type F
Function UART0 data input pin. This pin is used for input during UART0 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. General-purpose I/O port.
PE7 123 SO1 PF0 C
UART0 data output pin. This function is available when UART0 data output is enabled. General-purpose I/O port. This function is available when serial data output of UART0 is disabled.
124
SC1 PF1
F
UART0 clock I/O pin. This function is available when UART0 clock output is enabled. General-purpose I/O port. This function is available when UART0 clock output is disabled.
125
SI2
F
UART1 data input pin. This pin is used for input during UART1 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. General-purpose I/O port.
PF2 126 SO2 PF3 128, 129 INT4, INT5 I C
UART1 data output pin. This function is available when UART1 data output is enabled. General-purpose I/O port. This function is available when UART1 data output is disabled. External interrupt request input pins. These pins are used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from these pins unless such output is made intentionally. General-purpose I/O ports.
PF4, PF5 131, 132 134 PF6, PF7 DACK0 E C
I/O ports of open-drain type. Transfer request acknowledge output pin for DMAC (ch. 0). This function is available when transfer request output for DMAC is enabled. General-purpose I/O port. This function is available when transfer request for DMAC is disabled.
PG0
* : FPT-160P-M03
(Continued)
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MB91103 Series
Pin No. QFP* 135
Pin name DACK1
Circuit type I
Function External transfer request acknowledge output pin for DMAC (ch. 1). This function is available when transfer request output for DMAC is enabled. External interrupt request input pins. This pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. External trigger input pin for A/D converter. This pin is used for input when external trigger is selected to cause A/D converter operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. General-purpose I/O port. This function is available when transfer request acknowledge for DMAC is disabled.
INT6
ATG
PG1
136
DREQ0
F
External transfer request input pin for DMA (ch. 0). This pin is used for input when external trigger is selected to cause DMAC operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. General-purpose I/O port. External transfer request input pin for DMA (ch. 1). This pin is used for input when external trigger is selected to cause DMAC operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. External interrupt request input pins. This pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. General-purpose I/O port.
PG2 137 DREQ1 I
INT7
PG3 138 TI0 F
Input pin for reload-timer 0. This pin is used for input when input to reload-timer 0 is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. General-purpose I/O port. Output pin for reload-timer 0. This function is available when output from reload-timer is enabled. General-purpose I/O port. This function is available when output from reload-timer is disabled.
PG4 139 TO0 F
PG5
* : FPT-160P-M03
(Continued)
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MB91103 Series
Pin No. QFP* 141 TI1
Pin name
Circuit type F
Function Input pin for reload-timer 1. This pin is used for input when input to reload-timer is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. AIN input for up/down counter 0. This pin is used for input when input to the counter is enabled in phase-shift count mode or up/down count mode, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. General-purpose I/O port.
AIN0
PG6 142 T01 F
Input pin for reload-timer 1. This pin is used for input when input to reload-timer is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. BIN input for up/down counter 0. This pin is used for input when input to the counter is enabled in phase-shift count mode or up/down count mode, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. General-purpose I/O port. This function is available when output from reload-timer is disabled.
BIN0
PG7
143
IC0
F
Input pin for input capture 0 (ICU0). This pin is used for input when ICU is in edge detect operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. Clock I/O pin for UART1. This function is available when cock output of UART1 is enabled. ZIN-input for up/down counter 0. This pin is used for input when ZIN-input to the counter is enabled in by up/down counter 0, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. General purpose I/O port. This function is available when clock output of UART1 is enabled.
SC2
ZIN0
PH0
144
IC1
F
Input pin for input capture 1 (ICU1). This pin is used for input when ICU is in edge detect operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. AIN input for up/down counter 1. This pin is used for input when input to the counter is enabled in phase-shift count mode or up/down count mode, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. General-purpose I/O port.
AIN1
PH1 * : FPT-160P-M03
(Continued)
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MB91103 Series
Pin No. QFP* 145
Pin name IC2
Circuit type F
Function Input pin for input capture 2 (ICU2). This pin is used for input when ICU is in edge detect operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. BIN input for up/down counter 1. This pin is used for input when input to the counter is enabled in phase-shift count mode or up/down count mode, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. General-purpose I/O port.
BIN1
PH2 146 IC3 F
Input pin for input capture 3 (ICU3). This pin is used for input when ICU is in edge detect operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. ZIN-input for up/down counter 1. This pin is used for input when ZIN-input to the counter is enabled by up/down counter 1, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. General-purpose I/O port.
ZIN1
PH3 147 OC0 K
Output pin for output compare 0 (OCU0). This function is available when output of corresponding OCU is enabled. General-purpose I/O port. This function is available when output of corresponding OCU is disabled.
PH4
148
OC1
K
Output pin for output compare 1 (OCU1). This function is available when output of corresponding OCU is enabled. General-purpose I/O port. This function is available when output of corresponding OCU is disabled.
PH5
149
OC2
K
Output pin for output compare 2 (OCU2). This function is available when output of corresponding OCU is enabled. General-purpose I/O port. This function is available when output of corresponding OCU is disabled.
PH6
151
OC3
K
Output pin for output compare 3 (OCU3). This function is available when output of corresponding OCU is enabled. General-purpose I/O port. This function is available when output of corresponding OCU is disabled.
PH7
* : FPT-160P-M03 12
(Continued)
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MB91103 Series
(Continued)
Pin No. QFP* 152 Pin name OC4 Circuit type K Function Output pin for output compare 4 (OCU4). This function is available when output of corresponding OCU is enabled. General-purpose I/O port. This function is available when output of corresponding OCU is disabled. K Output pin for output compare 5 (OCU5). This function is available when output of corresponding OCU is enabled. General-purpose I/O port. This function is available when output of corresponding OCU is disabled. K Output pin for output compare 6 (OCU6). This function is available when output of corresponding OCU is enabled. General-purpose I/O port. This function is available when output of corresponding OCU is disabled. F Output pin for output compare 7 (OCU7). This function is available when output of corresponding OCU is enabled. General-purpose I/O port. This function is available when output of corresponding OCU is disabled. -- -- No connections allowed to this pin. Power supply pin (VCC) for digital circuit
PI0
153
OC5
PI1
154
OC6
PI2
155
OC7
PI3
130, 133 14, 24 46, 77 92, 140 160 9, 19 33, 51 73, 87 114, 127 150, 157 106 107
N.C. VCC
VSS
--
Earth level (VSS) for digital circuit.
AVCC AVRH
-- --
Power supply pin (VCC) for A/D converter. Reference voltage input (High) for A/D converter. Make sure to turn on and off this pin with potential of AVRH or more applied to VCC. Reference voltage input pin (Low) for A/D converter. Power supply pin (VSS) for A/D converter.
108 109 * : FPT-160P-M03
AVRL AVSS
-- --
Note: In most of the above pins, I/O port and resource I/O are multiplexed e.g. P82 and BRQ. In case of conflict between output of I/O port and resource I/O, priority is always given to the output of resource I/O. 13
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MB91103 Series
s DRAM CONTROL PIN
Pin name RAS0 RAS1 CS0L CS0H CS1L CS1H DW0 DW1 Data bus 32-bit mode Data bus 16-bit mode Data bus 8-bit mode -- Area 4 RAS Area 5 RAS Area 4 CAS
2
2CAS/1WE mode 1CAS/2WE mode 2CAS/1WE mode 1CAS/2WE mode Area 4 RAS Area 5 RAS CAS0 *1 CAS1 *
1
Area 4 RAS Area 5 RAS CAS CAS WE0 *1 WE1 *1 WE2 *1 WE3 *1
Area 4 RAS Area 5 RAS Area 4 CASL *2 Area 4 CASH *
2
Area 4 RAS Area 5 RAS Area 4 CAS Area 4 WEL * Area 5 CAS Area 5 WEL *2 Area 4 WEH *2 Area 5 WEH *2
Area 4 CAS Area 5 CAS Area 5 CAS Area 4 WE Area 5 WE
CAS2 *1 CAS3 *1 WE WE
Area 5 CASL *2 Area 5 CASH *2 Area 4 WE Area 5 WE
*1: 0, 1, 2 and 3 respectively corresponds to the lowest 2 bits of address as follows: 0: "00", 1: "01", 2: "10", 3: "11" *2: L and H respectively corresponds to the LSB of address as follows: L: "0", H: "1"
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MB91103 Series
s I/O CIRCUIT TYPE
Type A
X1 Clock input
Circuit
Remarks * Oscillation feedback resistance 1 M approx. With Standby control
X0
Standby control signal
B
VCC P-ch P-ch
* CMOS level hysteresis input Without standby control With pull-up resistance
R VSS
N-ch
Digital input
C
P-ch Digital output
* CMOS level I/O With standby control
R
N-ch
Digital output
Digital input Standby control signal
D
P-ch Digital output
* CMOS level I/O With standby control * Analog input
R
N-ch
Digital output
Analog input Digital input Standby control signal
(Continued)
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MB91103 Series
Type E
Circuit
Remarks * N-ch open-drain output * CMOS level output With standby control
Digital output
P-ch
R
N-ch
Digital input Standby control signal
F
P-ch
* CMOS level output * CMOS level hysteresis input With standby control
Digital output
R
N-ch
Digital input Standby control signal
G
P-ch N-ch
* CMOS level I/O Without standby control
R
Digital input
H
P-ch N-ch
* CMOS level hysteresis input Without standby control
R
Digital input
(Continued)
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MB91103 Series
(Continued)
Type I Circuit Remarks * CMOS level output * CMOS level hysteresis input Without standby control
P-ch N-ch Digital output
R
Digital output
Digital input
J
P-ch Digital output
* CMOS level output * TTL level input With standby control
R
N-ch
Digital output
Digital input Standby control signal TTL
K
P-ch Digital output
* CMOS level input/output With standby control * Large current drive
R
N-ch
Digital output
Digital input Standby control signal
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MB91103 Series
s HANDLING DEVICES
1. Preventing Latchup
In CMOS ICs, applying voltage higher than VCC or lower than VSS to input/output pin or applying voltage over rating across VCC and VSS may cause latchup. This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the device. Make sure to prevent the voltage from exceeding the maximum rating. For the same reason, make sure to prevent the analog power supply voltage (AVCC, AVR) and analog input from exceeding the digital power supply voltage when turning on/off the device.
2. Treatment of Unused Pins
Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors.
3. Remarks for External Clock Operation
When external clock is selected, stabilization time is necessary at the time of power reset (optional) or wakening up from stop mode. * Using an External Clock
X0 X1 MB91103
4. Power Supply Pins
When there are several VCC and VSS pins, each of them is geometrically connected to its counterpart inside of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions, to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to observe the total output current standard, connect each pin directly to VCC or VSS outside of the device. It is preferred to connect VCC and VSS of this device to power supply with minimal impedance possible. It is also recommended to connect a bypass capacitor of about 0.1 F between VCC and VSS at a position as close as possible to this device.
5. Crystal Oscillator Circuit
Noises around X0 and X1 pins may cause malfunctions of this device. In designing the PC board, lay out X0, X1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible. Prevent their wiring from being crossed by other wires. It is strongly recommended to design PC board so that X1 and X0 pins are surrounded by grounding area for stable operation. 18
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MB91103 Series
6. Turning-on Sequence of A/D Converter Power Supply and Analog Input
Make sure to turn on the digital power supply (VCC) before turning on the A/D converter (AVCC, AVRH, AVRL) and applying voltage to analog input (AN0 to AN7). Make sure to turn off digital power supply after power supply to A/D converters and analog inputs have been switched off. (There are no such limitations in turning on power supplies. Analog and digital power supplies may be turned on simultaneously.) Make sure that AVRH never exceeds AVCC when turning on/off power supplies.
7. Treatment of N.C. Pins
Make sure to leave N.C. (internal connection) pins open.
8. Fluctuation of Power Supply Voltage
Warranty range for normal operation against fluctuation of power supply voltage is as given in rating. However, sudden fluctuation of power supply voltage within the warranty range may cause malfunctions. It is recommended to make every effort to stabilize the power supply voltage.
9. Mode Setting Pins
Connect mode setting pins (MD0 to MD2) directly to VCC or VSS. Arrange each mode setting pin and VCC or VSS patterns on the printed circuit board as close as possible and make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises.
10. External Reset Input
Keep the RST pin level at "L" for at least 5 machine cycles to ensure proper reset operation.
11. I/O Access Limmitations When Using Gear Function
In MB91103 series, there are some limmitations concerning about accesses to the I/O area. Limitted I/O area: 0X10H to 0XFFH 0X400H to 0X5FFH
Clock gear combinations: Peripheral system CPU system 1/1 1/2 1/4 1/8 In the limitted clock gear combination shown in the above table, there are limitations concerning about accesses to the appricable I/O area as below. (1) When accessing to the I/O area, use only 16-bit length instruction or 8-bit length instruction. (2) When putting the read-out instruction from the appricable I/O area right after the write-in instruction to the same I/O area, put the dummy read-out instruction from the same area. : Without limitation : Limitted 1/1 1/2 1/4 1/8
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MB91103 Series
(Example) sth r 0, lduh @r4, lduh @r2, @r1 r3 r3 ; r1, r2, r4 are the appricable I/O areas ; Write-in instruction ; Dummy read-out instruction : add this instruction ; Target read-out insturction
0x400 address is recomendable for the dummy read-out instruction address. As interrupting controllers ICR00 and ICR01 are put in this address, there is no bad influence owing to dummy read-out operations.
12. DMAC Limitations When Using Gear Function
In MB91103 series, UART operated in synclonizing transfer mode must not be DMA transfer facter. Clock gear combinations: Peripheral system CPU system 1/1 1/2 1/4 1/8 : Without limitation : Prohibite to use 1/1 1/2 1/4 1/8
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MB91103 Series
s BLOCK DIAGRAM
FR20 CPU
I bus (16-bit)
DREQ0 DREQ1 DACK0 DACK1
D bus (32-bit)
Bit search module
Instruction cache
DMAC (5 ch.)
Bus converter (HarvardPrinceton)
Bus converter (32-bit16-bit)
32 24 4
X0 X1 RST HST
Clock control unit Bus controller 4 6 Interrupt control unit
C bus (32-bit)
INT0 to INT7 NMI
8
D00 to D31 A00 to A23 RD WR0 to WR3 RDY ACLK CLK ALE PAR0 to PAR3 CS0 to CS5 BRQ BGRNT
AN0 to AN7 ATG AVCC AVSS AVRH AVRL
8 A/D converter (8 ch.)
DRAM controller
TI0 TI1 TO0 TO1
Reload timer (2 ch.)
R bus (16-bit)
RAS0 RAS1 CS0L CS0H CS1L CS1H DW0 DW1 8 8 8 8 3 3 8 8 8 P00 to P07 P10 to P17 P20 to P27 P60 to P67 P80 to P82 P85 to P87 P90 to P95 PA0 to PA6 PB0 to PB7 SI1 SI2 SO1 SO2 SC1 SC2
AIN0 AIN1 BIN0 BIN1 ZIN0 ZIN1 PD0 to PD7 PE0 to PE7 PF0 to PF5 PG0 to PG7 PH0 to PH7 PI0 to PI3 8 8 6 8 8 4
Port 0 to port B Up-down counter
UART (2 ch.) Port D to Port I
U-TIMER (2 ch.) (Baud rate timer) SI0 SO0 SC0 4 8 IC0 to IC3 OC0 to OC7
Extended I/O serial interface Other pins VCC, VSS, MD0 to MD2 Real-time I/O time
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MB91103 Series
s CPU CORE
1. Memory Space
The FR20 series has a logical address space of 4 G bytes (232 bytes) and the CPU linearly accesses the memory space. The MB91103 has no internal memories (RAM, ROM).
* Memory space
MB91103 0000 0000H I/O area 0000 0400H See "s I/O MAP" I/O area 0000 0800H Direct addressing area
Access inhibited
0001 0000H External area 000C 0000H
External area
FFFF FFFFH
* Direct addressing area The following areas on the memory space are assigned to direct addressing area for I/O. In these areas, an address can be specified in a direct operand of a code. Direct areas consists of the following areas dependent on accessible data sizes. Byte data access: 0 to 0FFH Half word data access: 0 to 1FFH Word data access: 0 to 3FFH
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MB91103 Series
2. Registers
The FR20 series has two types of registers -- dedicated registers embedded on the CPU and general-purpose registers on memory. * Dedicated registers Program counter (PC) Program status (PS) Table base register (TBR) : 32-bit length, indicates the location of the instruction to be executed : 32-bit length, register for storing register pointer or condition codes : Holds top address of vector table used in EIT (Exceptional/Interrupt/Trap) processing. Return pointer (RP) : Holds address to resume operation after returning from a subroutine. System stack pointer (SSP) : Indicates system stack space. User's stack pointer (USP) : Indicates user's stack space. Multiplication/Division result register (MDH/MDL): 32-bit length, register for multiplication/division.
32 bits PC PS TBR RP SSP USP MDH MDL Program counter Program status Table base register Return pointer System stack pointer User's stack pointer
Initial value XXXX XXXXH
not fixed
000F
FC00H not fixed
XXXX XXXXH 0000 0000H
XXXX XXXXH XXXX XXXXH XXXX XXXXH
not fixed not fixed not fixed
Multiplication/division result register
The PS register is for holding program status and consists of a condition code register (CCR), a system condition code register (SCR) and a level mask register (ILM).
31 PS --
20
19
18
17
16 --
10 D1
9 D0
8 T
7 --
6 --
5 S
4 I
3 N
2 Z
1 V
0 C
ILM4 ILM3 ILM2 ILM1 ILM0
ILM
SCR
CCR
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MB91103 Series
* Condition code register (CCR) S flag : Specifies a stack pointer used as R15. I flag : Controls user interrupt request enable/disable. N flag : Indicates sign bit when division result is assumed to be in the 2's complement format. Z flag : Indicates whether or not the result of division was "0". V flag : Assume the operand used in calculation in the 2's complement format and indicates whether or not overflow has occurred. C flag : Indicates if a carry or borrow from the MSB has occurred. * System condition code register (SCR) T flag : Specifies whether or not to enable step trace trap. * Interrupt level mask register (ILM) ILM4 to ILM0 : Register for holding interrupt level mask value. The value held by this register is used as a level mask. When an interrupt request issued to the CPU is higher than the level held by ILM, the interrupt request is accepted. ILM4 0 ILM3 0 ILM2 0 : : 0 1 0 : : 1 1 1 1 1 0 0 ILM1 0 ILM0 0 Interrupt level 0 : : 15 : : 31 Low Priority High
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MB91103 Series
s GENERAL-PURPOSE REGISTERS
R0 to R15 are general-purpose registers embedded on the CPU. These registers functions as an accumulator and a memory access pointer (field for indicating address). User can specify the functions of the registers.
* Register bank structure
32 bits Initial value R0 R1 : : R12 R13 R14 R15 AC (Accumulator) FP (Frame Pointer) SP (Stack Pointer) XXXX XXXXH : : : : : : : : : : : XXXX XXXXH 0 0 0 0 0 0 0 0H
Of the above 16 registers, following registers have special functions. To support the special functions, part of the instruction set has been sophisticated to have enhanced functions. R13: Virtual accumulator (AC) R14: Frame pointer (FP) R15: Stack pointer (SP) Upon reset, values in R0 to R14 are not fixed. Value in R15 is initialized to be 00000000H (SSP value).
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MB91103 Series
s SETTING MODE
1. Pin
* Mode setting pins and modes Mode setting pins MD2 MD1 MD0 0 0 0 0 1 0 0 1 1 -- 0 1 0 1 -- External vector mode 0 External vector mode 1 External vector mode 2 Internal vector mode -- Mode name Reset vector access area External External External Internal -- External data bus width 8 bits 16 bits 32 bits (Mode register) -- Single-chip mode* Inhibited External ROM External bus mode Bus mode
* : MB91103 does not support single-chip mode.
2. Registers
* Mode setting registers and modes
Address 0000 07FFH M1 M0
Initial value XXXX XXXXB
Access W
Bus mode setting bit W : Write only X : Not fixed : Always write "0" except for M1 and M0.
* Bus mode setting bits and functions M1 0 0 1 1 M0 0 1 0 1 Single-chip mode Internal ROM external bus mode External ROM External bus mode -- Inhibited Functions Note
Note: For a device without internal ROM, set "10B" only. MB91103 allows "10B" setting only.
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MB91103 Series
s I/O MAP
Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH to 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H SDR SMCS SSR0 SIDR0/SODR0 SCR0 SMR0 SSR1 SIDR1/SODR1 SCR1 PDRD PDRE PDRF PDRG PDRH PDRI PDRB PDRA PDR9 PDR8 PDR6 PDR2 PDR1 PDR0 Register name (Abbreviated) Vacant Port 2 data register Port 1 data register Port 0 data register Vacant Port 6 data register Vacant Port B data register Port A data register Port 9 data register Port 8 data register Vacant Port D data register Port E data register Port F data register Port G data register Port H data register Port I data register Vacant Serial data register Serial mode control status register Serial status register 0 Serial input register 0/Serial output register 0 Serial control register 0 Serial mode register 0 Serial status register 1 Serial input register 1/Serial output register 1 Serial control register 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W XXXXXXXXB 00000010B ----0000B 00001-00B XXXXXXXXB 00000100B 00--0-00B 00001-00B XXXXXXXXB 00000100B R/W R/W R/W R/W R/W R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB - - - - XXXXB R/W R/W R/W R/W XXXXXXXXB -XXXXXXXB - -XXXXXXB XXX - - XXXB R/W XXXXXXXXB R/W R/W R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB Register name Read/write Initial value
(Continued)
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MB91103 Series
Address 0023H 0024H to 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH to 0044H 0045H 0046H 0047H 0048H 0049H 004AH 004BH
Register name (Abbreviated) SMR1
Register name Serial mode register 1 Vacant
Read/write R/W
Initial value 00--0-00B
TMRLR0
16-bit reload register ch. 0
W
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
TMR0
16-bit timer register ch. 0
R
Vacant 16-bit reload timer control status register ch. 0 16-bit reload register ch. 1 ----0000B 00000000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
TMCSR0
R/W
TMRLR1
W
TMR1
16-bit timer register ch. 1
R
Vacant 16-bit reload timer control status register ch. 1 A/D converter data register ----0000B 00000000B 0 0 0 0 0 0 XXB XXXXXXXXB 00000000B 00000000B
TMCSR1
R/W
ADCR
R
ADCS
A/D converter control status register
R/W
Vacant ICS0 Input capture control status register ch. 0 Vacant XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W 00000000B
IPCP0
Input capture data register 0
R
IPCP1
Input capture data register 1
R
(Continued)
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MB91103 Series
Address 004CH 004DH 004FH 004EH 0050H 0051H 0052H 0053H 0054H 0055H 0056H 0057H 0058H 0059H 005AH 005BH 005CH 005DH 005EH 005FH 0060H 0061H 0062H 0063H 0064H 0065H 0066H 0067H 0068H 0069H 006AH 006BH
Register name (Abbreviated) Vacant ICS1
Register name
Read/write
Initial value
Input capture control status register ch. 1 Vacant
R/W
00000000B
IPCP2
Input capture data register 2
R
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ---00000B 0000--00B
IPCP3
Input capture data register 3
R
OCS0
Output compare control status register ch. 0
R/W
Vacant XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ---00000B 0000--00B
OPCP0
Output compare register ch. 0
R/W
OPCP1
Output compare register ch. 1
R/W
OCS1
Output compare control status register ch. 1
R/W
Vacant XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ---00000B 0000--00B
OPCP2
Output compare register ch. 2
R/W
OPCP3
Output compare register ch. 3
R/W
OCS2
Output compare control status register ch. 2
R/W
Vacant XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
OPCP4
Output compare register ch. 4
R/W
OPCP5
Output compare register ch. 5
R/W
(Continued)
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MB91103 Series
Address 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0080H to 0083H 0084H 0085H 0086H 0087H 0088H 0089H 008AH 008BH 008CH 008DH
Register name (Abbreviated) OCS3
Register name Output compare control status register ch. 3
Read/write R/W
Initial value ---00000B 0000--00B
Vacant XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B
OPCP6
Output compare register ch. 6
R/W
OPCP7
Output compare register ch. 7
R/W
TCDT
16-bit free-run timer count data register Vacant
R/W
TCCS UTIM0/UTIMR0
16-bit free-run timer count control status register U-TIMER register ch. 0/Reload register ch. 0 Vacant
R/W R/W
00000000B 00000000B 00000000B
UTIMC0 UTIM1/UTIMR1
U-TIMER control register ch. 0 U-TIMER register ch. 1/Reload register ch. 1 Vacant
R/W R/W
0--00001B 00000000B 00000000B
UTIMC1
U-TIMER control register ch. 1 Vacant
R/W
0--00001B
UDCR0
16-bit up-down count register ch. 0 16-bit up/down counter reload/compare register ch. 0 16-bit up/down counter control register ch. 0 Vacant
R
00000000B 00000000B 00000000B 00000000B -0000000B -0001000B
RCR0
W
CCR0
R/W
CSR0 UDCR1
16-bit up/down counter status register ch. 0 16-bit up/down count register ch. 1
R/W R
00000000B 00000000B 00000000B
(Continued)
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MB91103 Series
Address 008EH 008FH 0090H 0091H 0092H 0093H 0094H 0095H 0096H 0097H 0098H 0099H 009AH to 00D0H 00D1H 00D2H 00D3H 00D4H 00D5H 00D6H 00D7H 00D8H to 01FFH 0200H 0201H 0202H 0203H 0204H 0205H 0206H 0207H
Register name (Abbreviated) RCR1
Register name 16-bit up/down counter reload/compare register ch. 1 16-bit up/down counter control register ch. 1 Vacant
Read/write W
Initial value 00000000B 00000000B -0000000B -0001000B
CCR1
R/W
CSR1 EIRR ENIR
16-bit up/down counter status register ch. 1 External interrupt cause register Interrupt enable register Vacant External interrupt request level setting register Vacant
R/W R/W R/W
00000000B 00000000B 00000000B
ELVR
R/W
00000000B 00000000B
DDRD DDRE DDRF DDRG DDRH DDRI AIC
Port D data direction register Port E data direction register Port F data direction register Port G data direction register Port H data direction register Port I data direction register Port D analog input control register Vacant
W W W W W W W
00000000B 00000000B 00000000B 00000000B 00000000B ----0000B 00000000B
0-000000B DMACS0 DMAC-ch. 0 control/status register R/W 000---X0B XXXXXXXXB XXXXXX - XB XXXXXXXXB DMACC0 DMAC-ch. 0 addressing/count setting register R/W - XXXXXXXB XXXXXXXXB XXXXXXXXB
(Continued)
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MB91103 Series
Address 0208H 0209H 020AH 020BH 020CH 020DH 020EH 020FH 0210H to 021FH 0220H 0221H 0222H 0223H 0224H 0225H 0226H 0227H 0228H 0229H 022AH 022BH 022CH 022DH 022EH 022FH 0230H 0231H 0232H 0233H
Register name (Abbreviated)
Register name
Read/write
Initial value 0-000000B
DMACS1
DMAC-ch. 1 control/status register
R/W
000---X0B XXXXXXXXB XXXXXX - XB XXXXXXXXB
DMACC1
DMAC-ch. 1 addressing/count setting register
R/W
- XXXXXXXB XXXXXXXXB XXXXXXXXB
Vacant 0-000000B DMACS4 DMAC-ch. 4 control/status register R/W 000-----B - - XXXXXXB - - - - XX - XB 0 0 0 0 XXXXB DMACC4 DMAC-ch. 4 addressing/count setting register R/W - XXXXXXXB XXXXXXXXB XXXXXXXXB 0-000000B DMACS5 DMAC-ch. 5 control/status register R/W 000-----B - - XXXXXXB - - - - XX - XB 0 0 0 0 XXXXB DMACC5 DMAC-ch. 5 addressing/count setting register R/W - XXXXXXXB XXXXXXXXB XXXXXXXXB 0-000000B DMACS6 DMAC-ch. 6 control/status register R/W 000-----B - - XXXXXXB - - - - XX - XB
(Continued)
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MB91103 Series
Address 0234H 0235H 0236H 0237H 0238H to 023FH 0240H 0241H 0242H 0243H 0244H 0245H 0246H 0247H 0248H 0249H 024AH 024BH 024CH 024DH 024EH 024FH 0250H 0251H 0252H 0253H 0254H 0255H 0256H 0257H
Register name (Abbreviated)
Register name
Read/write
Initial value 0 0 0 0 XXXXB
DMACC6
DMAC-ch. 6 addressing/count setting register
R/W
- XXXXXXXB XXXXXXXXB XXXXXXXXB
Vacant XXXXXXXXB DMAAR0 DMAC address register 0 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB DMAAR1 DMAC address register 1 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B DMAAR2 DMAC address register 2 R/W 0 0 0 0 0 XXXB XXXXXXXXB XXXXXXXXB 00000000B DMAAR3 DMAC address register 3 R/W 0 0 0 0 0 XXXB XXXXXXXXB XXXXXXXXB 00000000B DMAAR4 DMAC address register 4 R/W 0 0 0 0 0 XXXB XXXXXXXXB XXXXXXXXB 00000000B DMAAR5 DMAC address register 5 R/W 0 0 0 0 0 XXXB XXXXXXXXB XXXXXXXXB
(Continued)
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MB91103 Series
Address 0258H 0259H 025AH 025BH 025CH 025DH 025EH 025FH 0260H 0261H 0262H 0263H 0264H to 0267H 0268H 0269H 026AH 026BH 026CH 026DH 026EH to 0273H 0274H 0275H 0276H 0277H 0278H to 03E3H 03E4H 03E5H 03E6H 03E7H
Register name (Abbreviated)
Register name
Read/write
Initial value 00000000B
DMAAR6
DMAC address register 6
R/W
0 0 0 0 0 XXXB XXXXXXXXB XXXXXXXXB 00000000B
DMAAR7
DMAC address register 7
R/W
0 0 0 0 0 XXXB XXXXXXXXB XXXXXXXXB
DMACT0
DMAC transfer count register 0
R/W
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
DMACT1
DMAC transfer count register 1
R/W
Vacant 00000000B XXXXXXXXB 00000000B XXXXXXXXB 00000000B XXXXXXXXB
DMACT4
DMAC transfer count register 4
R/W
DMACT5
DMAC transfer count register 5
R/W
DMACT6
DMAC transfer count register 6
R/W
Vacant --------B DMACR DMAC total control register R/W --------B 00------B ----0000B Vacant --------B ICHCR Instruction cache control register R/W --------B --------B --000000B
(Continued)
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MB91103 Series
Address 03E8H to 03EFH 03F0H 03F1H 03F2H 03F3H 03F4H 03F5H 03F6H 03F7H 03F8H 03F9H 03FAH 03FBH 03FCH 03FDH 03FEH 03FFH 0400H 0401H 0402H 0403H 0404H 0405H 0406H 0407H 0408H 0409H 040AH 040BH 040CH 040DH
Register name (Abbreviated) Vacant
Register name
Read/write
Initial value
XXXXXXXXB BSD0 Bit search module 0-detection data register W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB BSD1 Bit search module 1-detection data register R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB BSDC Bit search module transition-detection data register W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB BSRR Bit search module detection result register R XXXXXXXXB XXXXXXXXB XXXXXXXXB ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 Interrupt control register 3 Interrupt control register 4 Interrupt control register 5 Interrupt control register 6 Interrupt control register 7 Interrupt control register 8 Interrupt control register 9 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B
(Continued)
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MB91103 Series
Address 040EH 040FH 0410H 0411H 0412H 0413H 0414H 0415H 0416H 0417H 0418H 0419H 041AH 041BH 041CH 041DH 041EH 041FH 0420H 0421H 0422H 0423H 0424H 0425H 0426H 0427H 0428H 0429H 042AH 042BH 042CH 042DH
Register name (Abbreviated) ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45
Register name Interrupt control register 14 Interrupt control register 15 Interrupt control register 16 Interrupt control register 17 Interrupt control register 18 Interrupt control register 19 Interrupt control register 20 Interrupt control register 21 Interrupt control register 22 Interrupt control register 23 Interrupt control register 24 Interrupt control register 25 Interrupt control register 26 Interrupt control register 27 Interrupt control register 28 Interrupt control register 29 Interrupt control register 30 Interrupt control register 31 Interrupt control register 32 Interrupt control register 33 Interrupt control register 34 Interrupt control register 35 Interrupt control register 36 Interrupt control register 37 Interrupt control register 38 Interrupt control register 39 Interrupt control register 40 Interrupt control register 41 Interrupt control register 42 Interrupt control register 43 Interrupt control register 44 Interrupt control register 45
Read/write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B ---11111B
(Continued)
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MB91103 Series
Address 042EH 042FH 0430H 0431H 0432H to 047FH 0480H 0481H 0482H 0483H 0484H 0485H 0486H to 0600H 0601H 0602H 0603H 0604H 0605H 0606H 0607H 0608H 0609H 060AH 060BH 060CH 060DH 060EH 060FH 0610H 0611H
Register name (Abbreviated) ICR46 ICR47 DICR HRCL
Register name Interrupt control register 46 Interrupt control register 47 Delayed interrupt control register Hold request cancel request level setting register Vacant Reset cause register/Watch-dog peripheral control register Standby control register DMA request squelch register Time-base timer clear register Gear control register Watch-dog reset occurrence postpone register Vacant
Read/write R/W R/W R/W R/W
Initial value ---11111B ---11111B -------0B ---11111B
RSRR/WTCR STCR PDRR CTBR GCR WPR
R/W R/W R/W W R/W W
1 - XXX - 0 0 B 000111--B ----0000B XXXXXXXXB 11--11-1B XXXXXXXXB
DDR2 DDR1 DDR0
Port 2 data direction register Port 1 data direction register Port 0 data direction register Vacant
W W W
00000000B 00000000B 00000000B
DDR6
Port 6 data direction register Vacant
W
00000000B
DDRB DDRA DDR9 DDR8 ASR1
Port B data direction register Port A data direction register Port 9 data direction register Port 8 data direction register Area select register 1
W W W W W
00000000B -0000000B --000000B 000--000B 00000000B 00000001B 00000000B 00000000B 00000000B 00000010B
AMR1
Area mask register 1
W
ASR2
Area select register 2
W
(Continued)
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MB91103 Series
Address 0612H 0613H 0614H 0615H 0616H 0617H 0618H 0619H 061AH 061BH 061CH 061DH 061EH 061FH 0620H 0621H 0622H 0623H 0624H 0625H 0626H 0627H 0628H 0629H 062AH 062BH 062CH 062DH 062EH 062FH 0630H to 07FDH
Register name (Abbreviated) AMR2
Register name Area mask register 2
Read/write W
Initial value 00000000B 00000000B 00000000B 00000011B 00000000B 00000000B 00000000B 00000100B 00000000B 00000000B 00000000B 00000101B 00000000B 00000000B ---00111B 0--00000B 00000000B 0--00000B 0--00000B 00000000B - - XXXXXXB 00---000B -1001100B -1111111B --------B 11111111B 00000000B 0000000-B 00000000B 0000000-B
ASR3
Area select register 3
W
AMR3
Area mask register 3
W
ASR4
Area select register 4
W
AMR4
Area mask register 4
W
ASR5
Area select register 5
W
AMR5 AMD0 AMD1 AMD32 AMD4 AMD5 DSCR RFCR
Area mask register 5 Area mode register 0 Area mode register 1 Area mode register 32 Area mode register 4 Area mode register 5 DRAM signal control register Refresh control register
W R/W R/W R/W R/W R/W W R/W
EPCR0
External pin control register 0
W
EPCR1
External pin control register 1
W
DMCR4
DRAM control register 4
R/W
DMCR5
DRAM control register 5
R/W
Vacant
(Continued)
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(Continued)
Address 07FEH 07FFH Register name (Abbreviated) LER MODR Register name Little endian register Mode register Read/write W W Initial value -----000B XXXXXXXXB
Note: Do not use vacant areas.
s INTERRUPT CAUSES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTER ALLOCATIONS
Interrupt causes Interrupt number HexaDecimal decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 Interrupt level *1 Setting register -- -- -- -- -- -- -- -- -- Fixed to 4 -- -- Fixed to 4 -- -- Fixed to 15 (FH) ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 Register address -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 00000400H 00000401H 00000402H 00000403H 00000404H 00000405H 00000406H 00000407H 00000408H Interrupt vector *2 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH Vector address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH
Reset *1 Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Reserved for system Co-processor unattended trap Co-processor error trap INTE instruction Instruction break exception Operand break trap Step trace trap Reserved for system Exception for undefined instruction NMI (user) request Parity error area 4 Parity error area 5 External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6
(Continued)
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MB91103 Series
Interrupt causes
Interrupt number HexaDecimal decimal 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37
Interrupt level *1 Setting register ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 Register address 00000409H 0000040AH 0000040BH 0000040CH 0000040DH 0000040EH 0000040FH 00000410H 00000411H 00000412H 00000413H 00000414H 00000415H 00000416H 00000417H 00000418H 00000419H 0000041AH 0000041DH 0000041CH 0000041DH 0000041EH 0000041FH 00000420H 00000421H 00000422H 00000423H 00000424H 00000425H 00000426H 00000427H
Interrupt vector *2 Offset 398H 394H 390H 38CH 388H 384H 380H 37CH 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H Vector address 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H
External interrupt 7 Reserved for system UART0 receive complete UART1 receive complete Reserved for system UART0 transmit complete UART1 transmit complete Reserved for system DMAC0 (complete, error) DMAC1 (complete, error) Reserved for system Reserved for system DMAC4 (complete, error) DMAC5 (complete, error) DMAC6 (complete, error) Reserved for system A/D (successive approximation type) Reload timer 0 Reload timer 1 U/D counter 0 U/D counter 1 ICU0 ICU1 ICU2 ICU3 OCU0 OCU1 OCU2 OCU3 OCU4 OCU5
(Continued)
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MB91103 Series
(Continued)
Interrupt number HexaDecimal decimal 56 57 58 59 60 61 62 63 64 65 66 to 255 38 39 3A 3B 3C 3D 3E 3F 40 41 42 to FF Interrupt level *1 Setting register ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 -- -- -- Register address 00000428H 00000429H 0000042AH 0000042BH 0000042CH 0000042DH 0000042EH 0000042FH -- -- -- Interrupt vector *2 Offset 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H to 000H Vector address 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H to 000FFD00H
Interrupt causes
OCU6 OCU7 U-TIMER 0 U-TIMER 1 Reserved for system I/O extended serial 16-bit free-run timer Delayed interrupt cause bit Reserved for system (used in REALOS *2) Reserved for system (used in REALOS *2) Used in INT instructions
*1: ICR sets an interrupt level corresponding to the interrupt request into a register provided in the interrupt controller. ICR is provided for each interrupt request. *2: Vector addresses are given by adding an offset value corresponding to each EIT (exception/interrupt/trap) cause to the TBR value. TBR (Table Base Register) holds the top address of EIT vector table. Default value (Initial value upon reset 000FFC00H) is used in "s Interrupt causes, interrupt vectors and interrupt control register allocations."
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MB91103 Series
s PERIPHERAL RESOURCES
1. I/O Ports
There are 2 types of I/O port register structure -- port data register (PDR0 to PDRI) and data direction register (DDR0 to DDRI, AIC), where bits PDR0 to PDR I and bits DDR0 to DDRI corresponds respectively. Each bit on the register corresponds to an external pin. In port registers input/output register of the port configures input/ output function of the port, while corresponding bit (pin) configures input/output function in data direction registers. Bit "0" specifies input and "1" specifies output. * For input (DDR = "0") setting; PDR reading operation: reads level of corresponding external pin PDR writing operation: writes set value to PDR * For output (DDR = "1") setting; PDR reading operation: reads PDR value PDR writing operation: outputs PDR value to corresponding external pin * Block diagram
Resource input
0
1 PDR read Data bus 0 PDR (Port data register) Resource output 1 Pin
Resource output enable DDR (Data direction register)
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* Port data register
Address 000003H 000002H 000001H 000005H 00000BH 00000AH 000009H 000008H 000011H 000012H 000013H 000014H 000015H 000016H bit 7 PDR0 PDR1 PDR2 PDR6 PDR8 PDR9 PDRA PDRB PDRD PDRE PDRF PDRG PDRH PDRI bit 0 Initial value XXXXXXXX B (R/W) XXXXXXXX B (R/W) XXXXXXXX B (R/W) XXXXXXXX B (R/W) XXX- - XXX B (R/W) - - XXXXXX B (R/W) - XXXXXXX B (R/W) XXXXXXXX B (R/W) XXXXXXXX B (R/W) XXXXXXXX B (R/W) XXXXXXXX B (R/W) XXXXXXXX B (R/W) XXXXXXXX B (R/W) - - - - XXXX B (R/W)
* Data direction register
Address 000603H 000602H 000601H 000605H 00060BH 00060AH 000609H 000608H 0000D1H 0000D2H 0000D3H 0000D4H 0000D5H 0000D6H 0000D7H bit 7 DDR0 DDR1 DDR2 DDR6 DDR8 DDR9 DDRA DDRB DDRD DDRE DDRF DDRG DDRH DDRI AIC* bit 0 Initial value 00000000 B (W) 00000000 B (W) 00000000 B (W) 00000000 B (W) 000- - 000 B (W) - - 000000 B (W) - 0000000 B (W) 00000000 B (W) 00000000 B (W) 00000000 B (W) 00000000 B (W) 00000000 B (W) 00000000 B (W) - - - - 0000 B (W) 00000000 B (W)
Access type(s) in parenthesis R/W : Read and write access type W : Write only : Vacant X : Not fixed * : A/D converter input/general-purpose input port selective by port D input
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2. DMA Controller (DMAC)
The DMA controller is a module embedded in FR 20 series devices, and performs DMA (Direct Memory Access) transfer. DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to enhanced performance of the system.
* Block diagram
DREQ0 DREQ1
External transfer request input External transfer input
External input setting Setting request for each channel Setting transfer mode for each channel Priority setting for each channel
Input setting register Request setting register Mode setting register
Peripheral interrupt request Peripheral interrupt request : :
Transfer request processing Request for each channel Request arbitration Priority judgment Control Transfer ch. decision Transfer start request ch. specification
Channel setting register Address control register Specified I/O
Hold request Hold control
Fixed address generation Address Address counter
ACK Transfer state machine (bus control) Address/count Count control
Address register group
Complete
Interrupt control Data control
Count
Transfer count counter
Count register group
Data buffe
FR20 CPU
44
D-BUS
Address generation control for each channel
I/O access control
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MB91103 Series
* Registers
Address 00000200H 00000204H 00000208H 0000020CH 00000220H 00000224H 00000228H 0000022CH 00000230H 00000234H 00000240H 00000244H 00000248H 0000024CH 00000250H 00000254H 00000258H 0000025CH 00000260H 00000262H 00000268H 0000026AH 0000026CH 00000274H DMACT6 *2 DMACR *1 DMACT4 *2 DMACT5 *3 DMACT0 DMACT1 bit 31 bit 16 DMACS0 DMACC0 DMACS1 DMACC1 DMACS4 DMACC4 DMACS5 DMACC5 DMACS6 DMACC6 DMAAR0 DMAAR1 DMAAR2 *1 DMAAR3 *1 DMAAR4 *1 DMAAR5 *1 DMAAR6 *1 DMAAR7 *1 bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
*1: 32-bit length, fix upper 16 bits except for the least-significant 3 bits to "0". bit 31 bit 16 bit 0 00000000 00000 B XXX B Fixed *2: 16-bit length, fix upper 8 bits to "0". bit 16 bit 8 00000000 B Fixed *3: 16-bit length, fix lower 8 bits to "0". bit 16 bit 8 bit 0 00000000 B Fixed bit 0
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MB91103 Series
3. UART
The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK synchronous communication. The MB91103 consists of 2 channels of UART. * Block diagram
Control signals Receive interrupt (To CPU) SC (Clock) Transmit clock From U-TIMER Clock select circuit Receive clock Transmit interrupt (To CPU)
From external clock SCI Receive control circuit Transmit control circuit
SI (Receive data)
Start bit detect circuit
Transmit start circuit
Receive bit counter
Transmit bit counter
Receive parity counter
Transmit parity counter
SO (Transmit data)
Receive status judge circuit
Receive shifter
Transmit shifter
Receive error generate signal for DMA (To DMAC)
Receive complete SIDR
Transmit start SODR
R - BUS
MD1 MD0 SMR register CS0 SCKE SOE SCR register
PEN P SBL CL A/D REC RXE TXE
SSR register
PE ORE FRE RDRF TDRE RIE TIE
Control signals
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MB91103 Series
* Registers
Address 0000001EH 00000022H 0000001FH 00000023H 0000001CH 00000020H 0000001DH 00000021H
bit 15 SCR0 SCR1
bit 8
bit 0
Initial value 00000100 00000100
B
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
B
SMR0 SMR1 SSR0 SSR1 SIDR0/SODR0 SIDR1/SIDR1
00 - - 0 - 00 00 - - 0 - 00 00001 - 00 00001 - 00 XXXXXXXX XXXXXXXX
B
B
B
B
B
B
Access type(s) in parenthesis R/W : Read and write access type - : Vacant X : Not fixed
4. I/O Extended Serial Interface
This block is a serial interface of 8-bit x 1 structure enabling clock synchronous data transfer. Data transfer format of LSB first or MSB first can be selected. DMA transfer operation is enabled by interrupt request. There are two serial I/O operating modes. Internal shift clock mode : In this mode, data transfer operation is synchronized with internal clock. It can be selected from 10/20/80/160/320 frequency division of machine clock. External shift clock mode : In this mode, data transfer operation is synchronized with clock input from external pin (SC0). Data transfer by CPU instructions is enabled when the general port sharing the external pin (SC0) is so configured.
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* Block diagram
R - BUS
(MSB first) D0 to D7 SI0 SDR (serial data register) SO0
D7 to D0 (LSB first) Transfer direction select Read Write
SC0 Control circuit Shift clock counter
Internal clock
2 SMD2 SMCS
1 SMD1
0 SMD0 SIE SIR BUSY STOP STRT MODE BDS SOE SCOE
Interrupt request R - BUS
* Registers
Address 0000001AH 00000019H
bit 15
bit 8 SMCS SDR
bit 0
Initial value 00000010 - - - - 0000 XXXXXXXX
B B B
(R/W) (R/W) (R/W)
Access type(s) in parenthesis R/W : Read and write access type - : Vacant X : Not fixed
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MB91103 Series
5. U-TIMER (16-bit timer for UART baud rate generation)
The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and reload value of U-TIMER allows flexible setting of baud rate. The U-TIMER operates as an interval timer by using interrupt issued on counter underflow. The MB91103 has 2 channel U-TIMER embedded on the chip. By combining 2 interval timers in cascade, an interval of up to 232 x can be counted.
* Block diagram
15 0
U-TIMER (reload register)
Load 15 0
UTIM ( U-TIMER register) Underflow (Peripheral clock) Clock Control MUX ch. 0 only f.f. Underflow To UART
* Registers
Address 00000078H 0000007CH 0000007BH 0000007FH
bit 15 UTIM0/UTIMR0 UTIM1/UTIMR1 UTIMC0 UTIMC1
bit 0
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
B B B B B
(R/W) (R/W) (R/W) (R/W)
0 - - 00001 0 - - 00001
B
Access type(s) in parenthesis R/W : Read and write access type - : Vacant X : Not fixed
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MB91103 Series
6. 16-bit Reload Timer
The 16-bit timer consists of a 16-bit down counter, a 16-bit reload timer, a pre-scaler for generating internal count clock and control registers. Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock) or external clock. The input/output pin (TO) outputs a deleted toggle wave on every underflow in the reload mode and outputs a square wave indicating the timer is in counting operation in the one-shot mode. The input pin (TI) is configured as an event input in the event count mode, a trigger input in the internal clock mode and also operates as a gate input. The external event count function in the reload mode can operate as a external clock divider. The MB91103 consists of 2 channels of 16-bit reload timer.
* Block diagram
16 TMRLR 0, TMRLR 1 (16-bit reload register)
8
Reload
TMCSR1 RELD
16-bit down counter UF 16 2 R-BUS GATE TMCR0 CSL1 Clock selector CSL0 OUT CTL. 2
OUTE OUTL INTE UF CNTE TRG IRQ
2 IN CTL. EXCK - 21 -- 23 25 3 Pre-scaler clear
Retrigger Port (TI) Port (TO)
TMCR0 MOD2 MOD1
Internal clock MOD0
3
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MB91103 Series
* Registers
Address 0000002EH 00000036H 0000002AH 00000032H 00000028H 00000030H
bit 15 TMCSR0 TMCSR1 TMR0 TMR1 TMRLR0 TMRLR1
bit 0
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
B B B B B B B B B B B B
(R/W) (R/W) (R) (R) (W) (W)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Access type(s) in parenthesis R/W : Read and write type R : Read only W : Write only - : Vacant X : Not fixed
7. Real Time Input/Output Timer
The 16-bit input/output timer consists of a 16-bit free-run timer, 8 output compares and 4 input capture modules. By using these functions, 8 independent wave outputs based on the 16-bit free-run timer as well as input pulse width measurement and external clock cycle measurement can be realized.
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* Block diagram
Control logic
16-bit free-run timer 16-bit timer Clear Output compare 0 Compare register 0
To each block
Toggle output
OC0
Compare register 1 Toggle output
OC1
Output compare 1 Compare register 2 Toggle output OC2
Compare register 3
R-BUS
Toggle output
OC3
Output compare 2 Compare register 4 Toggle output OC4
Compare register 5 Toggle output
OC5
Output compare 3 Compare register 6 Toggle output OC6
Compare register 7 Toggle output OC7
Input capture 0 Capture register 0 Edge select IC0
Capture register 1 Input capture 1 Capture register 2
Edge select
IC1
Edge select
IC2
Capture register 3 Interrupt 13
Edge select
IC3
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MB91103 Series
(1) 16-bit Free-Run Timer The 16-bit free-run timer consists of a 16-bit up/down counter and a control status register. Count value of this timer is used in output compare and input capture blocks as a basic time. * Count clock can be selected from 4 types of frequencies (/4, /16, /32, /64). * Interrupt can be issued upon count overflow. * Selecting a mode and setting the count value as equaling to the value of compare register "0" initializes the counter. * Block diagram
Interrupt request TCCS IVF IVFE STOP MODE CLR CLK1 CLK0 Divider
R-BUS
Comparator 0
16-bit up counter
Clock T15 to T00 Count value output
* Registers
Address 00000074H 00000077H
bit 15
bit 8 TCDT TCCS
bit 0
Initial value 00000000 B 00000000 B 00000000 B (R/W) (R/W)
Access type(s) in parenthesis R/W : Read and write access type
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MB91103 Series
(2) Output Compare The output compare consists of a 16-bit compare register, compare output pin block and a control register. When the value set in the compare register matches with the 16-bit free-run timer value, output level is reversed, enabling an interrupt request to be issued. * 8 compare registers can operate independently. A pair of compare registers can be used for controlling output pin levels. * Initial output level of output pins can be specified. * An interrupt is issued when compare value matches with timer value. * Block diagram
16-bit timer counter value (T15 to T00)
Compare control
Toggle output OTE0 CMOD OC0
Compare register 0 (2 ch., 4 ch., 6 ch.) (OPCP0, OPCP1)
R-BUS
16-bit timer counter value (T15 to T00) Toggle output Compare control OTE1 Compare register 1 (3 ch., 5 ch., 7 ch.) (OPCP2, OPCP3) OCS ICP1 ICP0 ICE1 ICE0 OC1
Control block To each control block
Compare 1 interrupt Compare 0 interrupt
Combinations of compare register 0 and 1: ch.0, ch.1/ch.2, ch.3/ch.4, ch.5/ch.6, ch.7
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* Registers
Address 00000058H 0000005AH 00000060H 00000062H 00000068H 0000006AH 00000070H 00000072H 00000054H 0000005CH 00000064H 0000006CH
bit 15 OPCP0 OPCP1 OPCP2 OPCP3 OPCP4 OPCP5 OPCP6 OPCP7 OCS0 OCS1 OCS2 OCS1
bit 0
Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX - - - 00000 0000 - - 00 - - - 00000 0000 - - 00 - - - 00000 0000 - - 00 - - - 00000 0000 - - 00
B B B B B B B B B B B B B B B B B B B B B B B B
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access type(s) in parenthesis R/W : Read and write access type - : Vacant X : Not fixed
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(3) Input Capture The input capture consists of input capture data registers and input capture control status registers. The input capture detects a rising edge, a falling edge or both edges of external input signal and hold the 16-bit free-run timer value at the moment into the register. The input capture can issue an interrupt upon edge detection, if enabled. Every input capture has a corresponding output pin. * Effective edge of external input can be selected from rising, falling or both edges. * The input capture issues an interrupt upon detection of an effective edge, if enabled. * Block diagram
16-bit timer counter value (T15 to T00)
Input capture data register 0, 2 (IPCP0, IPCP2)
Edge detect
ICO ICS1
R-BUS
16-bit timer counter value (T15 to T00)
EG11
EG10
EG01
EG00
Input capture data register 1, 3 (IPCP1, IPCP3)
Edge detect
IC1
ICP1
ICP0
ICE1
ICE0 Interrupt
Interrupt
* Registers
Address 00000048H 0000004AH 00000050H 00000052H 00000045H 0000004DH Access type(s) in parenthesis R/W : Read and write access type R : Read only X : Not fixed bit 15 bit 8 IPCP0 IPCP1 IPCP2 IPCP3 ICS0 ICS1 bit 0 Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000 00000000
B B B B B B B B
(R) (R) (R) (R) (R/W) (R/W)
B
B
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MB91103 Series
8. Up/down Counter
The up/down counter consists of 3 event input pins, a 16-bit up/down counter, 16-bit reload/compare register and peripheral circuits (control/status register) controlling these functions. The MB91103 consists of 2 channels of counter/timer.
* Block diagram
R - BUS CCR CGE1 CGE0 CGSC RCR 0, RCR 1 (reload/compare register) CTUT ZIN Edge/level detect UCRE RLDE Reload control
UDCC
Counter clear
UDCR 0, UDCR 1 (up/down count register) CMPF UDFF CCR CMS1 CMS0 CES1 CES0 Count clock AIN BIN Up/down count clock select UDIE OVFF
UDF1
UDF0
CDCF
CFIE
CITE
Pre-scaler
CSTR
CLKS Interrupt request Convert direction Over/underflow compare
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* Registers
Address 00000084H 0000008CH 00000086H 0000008EH 0000008BH 00000093H 00000088H 00000090H
bit 15
bit 8 UDCR0 UDCR1 RCR0 RCR1 CSR0 CSR1 CCR0 CCR1
bit 0
Initial value 00000000 B 00000000 B 00000000 B 00000000 B 00000000 B 00000000 B 00000000 B 00000000 B 00000000 B 00000000 B - 0000000 B - 0001000 B - 0000000 B - 0001000 B (R) (R) (W) (W) (R/W) (R/W) (R/W) (R/W)
Access type(s) in parenthesis R/W : Read and write access type R : Read only W : Write only - : Vacant
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MB91103 Series
9. Bit Search Module
The bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and returns locations of the transitions.
* Block diagram
Input latch
Address decoder
Detection mode
D-BUS
Single-detection data recovery
Bit search circuit
Search result
* Registers
Address 000003F0H 000003F4H 000003F8H 000003FCH
bit 31
bit 16 BSD0 BSD1 BSDC BSRR
bit 0
Initial value XXXXXXXX XXXXXXXX B XXXXXXXX XXXXXXXX B XXXXXXXX XXXXXXXX B XXXXXXXX XXXXXXXX B XXXXXXXX XXXXXXXX B XXXXXXXX XXXXXXXX B XXXXXXXX XXXXXXXX B XXXXXXXX XXXXXXXX B (W) (R/W) (W) (R)
Access type(s) in parenthesis R/W : Read and write access type R : Read only W : Write only
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MB91103 Series
10. A/D Converter
The A/D converter converts an analog input voltage to a digital value.
* Block diagram
AVCC AVR AVSS
Internal voltage generator MPX AN0 AN1 Input circuit AN2 Analog input AN4 AN5 AN6 R-BUS Decoder Data register ADCR ADCS A/D control register Trigger start ATG TIM0 (internal connection) (Reload timer ch.0) (Peripheral clock) Timer start Operating clock Pre-scaler bit 0 ADCS ADCR Initial value 00000000 00000000 0 0 0 0 0 0XX XXXXXXXX
B B B B
AN3
Successive approximation register
Comparator
AN7
Sample & hold circuit
* Registers
Address 0000003AH 00000038H Access type(s) in parenthesis R/W : Read and write access type R : Read only X : Not fixed bit 15
(R/W) (R)
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MB91103 Series
11. Interrupt Controller
The interrupt controller processes interrupt acknowledgments and arbitration between interrupts.
* Block diagram
INT0*2
IM
OR NMI NMI processing 4 Level judgment RI00 * * * RI47 (DLYIRQ) DLY1*1 * * * ICR00 * * ICR47
Priority judgment 5 LEVEL4 to LEVEL0*4 HLDREQ cancel request
HLDCAN*3
6 Vector judgment
Level vector generation
VCT5 to VCT0*5
R - BUS
*1: DLY1 stands for delayed interrupt module (delayed interrupt generation block). *2: INT0 is a wake-up signal to clock control block in the sleep or stop status. *3: HLDCAN is a bus release request signal for bus masters other than CPU. *4: LEVEL5 to LEVEL0 are interrupt level outputs. *5: VCT5 to VCT0 are interrupt vector outputs.
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MB91103 Series
* Registers
Address 00000400H 00000401H 00000402H 00000403H 00000404H 00000405H 00000406H 00000407H 00000408H 00000409H 0000040AH 0000040BH 0000040CH 0000040DH 0000040EH 0000040FH 00000410H 00000411H 00000412H 00000413H 00000414H 00000415H 00000416H 00000417H 00000418H 00000419H bit 7 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 bit 0 Initial value - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) Address 0000041AH 0000041BH 0000041CH 0000041DH 0000041EH 0000041FH 00000420H 00000421H 00000422H 00000423H 00000424H 00000425H 00000426H 00000427H 00000428H 00000429H 0000042AH 0000042BH 0000042CH 0000042DH 0000042EH 0000042FH 00000431H 00000430H bit 7 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 HRCL DICR bit 0 Initial value - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - 11111 B (R/W) - - - - - - - 0 B (R/W)
Access type(s) in parenthesis R/W : Read and write access type - : Vacant
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12. External Interrupt/NMI Control Block
The external interrupt/NMI control block controls external interrupt request signals input to NMI and INT0 to INT 7 pins. Detecting levels can be selected from "H", "L", rising edge and falling edge (not for NMI). INT1 and INT0 can be used as a DMA request signal.
* Block diagram
8 Interrupt enable register (ENIR) 9 R-BUS Gate 8 Interrupt cause register (EIIR) 8 Request level setting register (ELVR) Cause F/F Edge detection circuit 9 INT0 to INT7 NMI
Interrupt request
* Registers
Address 00000095H 00000094H 00000098H
bit 15
bit 8 ENIR EIRR ELVR
bit 0
Initial value 00000000 B 00000000 B 00000000 B 00000000 B (R/W) (R/W) (R/W)
Access type(s) in parenthesis R/W : Read and write access type
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13. Clock Generation/control Block
The clock generation/control block consists of the following 6 blocks: * CPU clock generation (including gear function) * Peripheral clock generation (including gear function) * Reset generation and cause hold * Standby function * DMA request prohibit * PLL (duty ratio adjustment circuit included) * Block diagram
[Clock generation/gear control block] Gear control register (GCR) CPU gear
R-BUS
Peripheral gear Internal clock 1/2 PLL CPU clock Internal bus clock Peripheral DMA clock Internal peripheral clock
X0 X1
Oscillator circuit
Selection circuit
Generation circuit
Internal interrupt request Internal reset
[Stop/sleep control block]
Standby control register (STCR) Status transition CPU hold enable Reset generation F/F Stop state Sleep state CPU hold request Control circuit Internal reset
[DMA prohibit circuit] DMA request DMA request prohibit register (PDRR) [Reset cause circuit] Power on sel
RST pin
Reset cause register (RSRR) [Watch-dog control block] Watch-dog reset generation postpone register (WPR) Watch-dog cycle control register (WTCR) Time-base timer clear register (CTBR) Time-base timer Count clock
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* Registers
Address 00000480H 00000481H 00000482H 00000483H 00000484H 00000485H
bit 15 RSRR/WTCR
bit 8
bit 0
Initial value 1 - XXX - 0 0
B
(R/W) (R/W) (R/W) (W) (R/W) (W)
STCR PDRR CTBR GCR WPR
000111 - - - - - 0000 XXXXXXXX 11 - - 11 - 1 XXXXXXXX
B
B
B
B
B
Access type(s) in parenthesis R/W : Read and write access type W : Write only - : Vacant X : Not fixed
14. DRAM Controller
The DRAM controller controls interface between CPU and DRAM. This function is active only when DRME bit of AMD4, AMD5 are set to "1". The DMCR register also controls parity check functions. This function is active other than the DRAM interface.
* Registers
Address 0000062CH 0000062EH
bit 15 DMCR4 DMCR5
bit 0
Initial value 00000000 B 0000000 - B 00000000 B 0000000 - B (R/W) (R/W)
Access type(s) in parenthesis R/W : Read and write access type - : Not used
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MB91103 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = 0.0 V) Parameter Power supply voltage Analog supply voltage *
1
Symbol VCC AVCC AVRH AVRL VI VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg
Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -- -- -- -- -- -- -- -- -- -10 -55 Max. VSS + 7.0 VSS + 7.0 VSS + 7.0 VSS + 7.0 VCC + 0.3 VCC + 0.3 10 8 100 50 -10 -4 -50 -20 990 +70 +150
Unit V V V V V V mA mA mA mA mA mA mA mA mW C C
Remarks
Analog reference voltage *1 Analog reference voltage *1 Input voltage *
2
Output voltage *2 "L" level maximum output current *3 "L" level average output current *
4
"L" level maximum total output current "L" level average total output current *5 "H" level maximum output current * "H" level average output current *
4 3
"H" level maximum total output current "H" level average total output current *5 Power dissipation Operating temperature Storage temperature
*1: Make sure that the voltage does not exceed VCC + 0.3 V. Make sure AVCC does not exceed VCC when turning on the device. *2: VI and VO must not exceed VCC + 0.3 V. *3: Maximum output current is a peak current value measured at a corresponding pin. *4: Average output current is an average current for a 100 ms period at a corresponding pin. *5: Average total output current is an average current for a 100 ms period for all corresponding pins. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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2. Recommended Operating Conditions
(VSS = 0.0 V) Parameter Symbol Value Min. 4.5 Power supply voltage Analog supply voltage Analog reference voltage Operating temperature VCC AVCC AVRH AVRL TA 3.0 VSS - 0.3 AVRL AVSS -10 Max. 5.5 5.5 VCC + 0.3 AVCC AVRH +70 Unit V V V V V C Remarks Normal operation Retaining the RAM state in stop mode
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VCC (V) Normal operation warranty range (TA = -10C to +70C) 5.5 4.5 Supply voltage
0 fCP/fCPP (MHz)
0.625 Internal clock
25
fCP/fCPP (MHz)
PLL system 25
Divide-by-2 system
0.625 FC (MHz)
Internal clock 1.25 0
10
25 Source oscillating clock
50
Note: * Use external clock if source oscillating clock > 25 MHz. * PLL oscillation stabilizing period > 100 s
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
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3. DC Characteristics
(VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter Symbol VIH "H" level input voltage VIHS VIHT VIHM VIL "L" level input voltage VILS VILT VILM Open-drain output pin application voltage "H" level output voltage VD Pin name Input other than following symbols *1 *2 MD0 to MD2 Input other than following symbols *1 *2 MD0 to MD2 PF6, PF7 D00 to D23 A00 to A31 P8 to PI (Except for PF6, PF7) D00 to D31 A00 to A23 P8 to PI (Except for PF6, PF7) (Except for PH4 to PH7) (Except for PI0 to PI2) PH4 to PH7 PI0 to PI2 PF6, PF7 D00 to D31 A00 to A23 P8 to PI RST Condition -- -- -- -- -- -- -- -- -- Min. 0.7 VCC 0.8 VCC 2.2 VCC - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 Value Typ. -- -- -- -- -- -- -- -- -- Max. VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.3 VCC 0.2 VCC 0.8 VSS + 0.3 VCC + 0.3 Unit V V V V V V V V V Hysteresis input TTL level Hysteresis input TTL level Remarks
VOH
VCC = 4.5 V IOH = -4.0 mA
4.0
--
--
V
VOL1 "L" level output voltage VOL2 VOLD Input leakage current (Hi-Z output leakage current)
VCC = 4.5 V IOL = 8.0 mA
--
--
0.4
V
VCC = 4.5 V IOL = 12.0 mA VCC = 4.5 V IOL = 4.0 mA VCC = 5.5 V 0.45 V < VI < VCC VCC = 5.5 V VI = 0.45 V FC = 25 MHz VCC = 5.5 V FC = 25 MHz VCC = 5.5 V --
-- --
-- --
0.4 0.4 5
V V A
ILI
--
--
Pull-up resistance RPULL Power supply current ICC
25 -- -- --
50 -- -- 10
100 180 100 --
k mA mA pF Sleep mode
VCC ICCS Except for VCC, VSS, AVCC, AVSS
Input capacitance CIN
*1: Hysteresis input pins :HST, NMI, PE0 to PE4, PE6, PE7, PF1, PF2, PF4, PF5, PG1 to PG3, PH0 to PH3, RST *2: TTL level input pins :D00 to D31, RDY, BRQ, PAR0 to PAR3 69
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MB91103 Series
4. AC Characteristics
(1) Clock Timing Rating (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter Clock frequency Clock cycle time Frequency shift ratio (when locked) *1 Input clock pulse width Input clock rising/falling time Internal operating clock frequency Pin Symbol name Condition FC tC f PWH PWL tCR tCF fCP fCPP tCP Internal operating clock cycle time tCPP X0 X1 X0 X1 -- X0 X0 -- -- -- -- -- Value Min. Max. 10 20 -- 8.5 -- 0.625 *2 0.625 *2 40 40 50 100 5 -- 8 25 25 1600 *2 1600 *2 Unit MHz ns % ns ns tCR + tCF Remarks
MHz CPU system MHz ns ns Peripheral system CPU system Peripheral system
*1: Frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock multiplication system.
+ +
f
=
|| x 100 (%) f0
Center frequency f 0 - -
*2: These values are for a minimum clock of 10 MHz input to X0, a divide-by-2 system of the source oscillation and a 1/8 gear. * AC rating measurement conditions
Output pin C = 80 pF
tC 0.8 VCC 0.2 VCC PWH tCF PWL tCR
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(2) Clock Output Timing (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter Cycle time CLK CLK CLK CLK Symbol Pin name tCYC tCHCL tCLCH CLK CLK CLK -- Condition Value Min. tCP 1/2 x tCYC - 10 1/2 x tCYC - 10 Max. -- 1/2 x tCYC + 10 1/2 x tCYC + 10 Unit ns ns ns Remarks *1 *2 *3
*1: tCYC is a frequency for 1 clock cycle including a gear cycle. *2: This rating is for a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n of the following equations with 1/2, 1/4, 1/8, respectively. * Min. : (1 - n/2) x tCYC - 10 * Max. : (1 - n/2) x tCYC + 10 *3: This rating is for a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n of the following equations with 1/2, 1/4, 1/8, respectively. * Min. : n/2 x tCYC - 10 * Max. : n/2 x tCYC + 10
tCYC tCHCL CLK 2.4 V 0.8 V tCLCH 2.4 V
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The relation between X0 input and clock output for configured by CHC/CCK1/CCK0 settings of GCR (Gear control register) is as follows:
X0 input
(1) Source oscillation x 1 (CHC bit of GCR set to "0") (a) Gear x 1 clock output CCK1/0: "00" tCYC
(b) Gear x 1/2 x clock output CCK1/0: "01" (c) Gear x 1/4 clock output CCK1/0: "10" (d) Gear x 1/8 clock output CCK1/0: "11"
tCYC
tCYC
tCYC
(2) Source oscillation x 1/2 (CHC bit of GCR set to "1") (a) Gear x 1 clock output CCK1/0: "00" tCYC
(b) Gear x 1/2 clock output CCK1/0: "01" (c) Gear x 1/4 clock output CCK1/0: "10" (d) Gear x 1/8 clock output CCK1/0: "11"
tCYC
tCYC
tCYC
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* Ceramic oscillator applications
Recommended circuit (2 contacts)
Recommended circuit (3 contacts)
X0 (158) *
X1 (159)
X0 (158) *
X1 (159)
C1
C2
C1
C2
C1, C2 internally connected.
* : Murata Mfg. Co., Ltd.
* Discreet type Frequency range [MHz] CSA CST 13.01 to 15.99 CSA CST 16.00 to 19.99 CSA Circuit parameter Model MTZ MTW MXZ040 MXW0C3 MXZ040 C1 [pF] 30 (30) 15 (15) 10 5 (5) C2 [pF] 30 (30) 15 (15) 10 5 (5) Rf *1 [] -- -- -- -- -- -- -- Rd *2 [] 0 0 0 0 0 0 0 Contact type 2 contacts 3 contacts 2 contacts 3 contacts 2 contacts 3 contacts 2 contacts 3 contacts
10.00 to 13.00
CSA CST MXZ040 MXW0H1
20.00 to 25.00
*1: Feed-back resistance Rf internally connected in LSI. *2: No damping resistance required. ( ): C1 and C2 internally connected.
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* SMD type Frequency range [MHz] CSACS CSTCS 13.01 to 15.99 CSACS CSTCS 16.00 to 19.99 CSACS CSTCS 20.00 to 25.00 CSACS CSTCS Circuit parameter Model MT MT MX040 MX0C3 MX040 MX0C2 MX040 MX0H1 C1 [pF] 30 (30) 15 (15) 10 (10) 5 (5) C2 [pF] 30 (30) 15 (15) 10 (10) 5 (5) Rf *1 [] -- -- -- -- -- -- -- -- Rd *2 [] 0 0 0 0 0 0 0 0 Contact type 2 contacts 3 contacts 2 contacts 3 contacts 2 contacts 3 contacts 2 contacts 3 contacts
10.00 to 13.00
*1: Feed-back resistance Rf internally connected in LSI. *2: No damping resistance required. ( ): C1 and C2 internally connected. (3) Reset Input (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter Reset input time Symbol Pin name Condition tRSTL RST -- Value Min. tCP x 5 Max. -- Unit ns Remarks
tRSTL
RST
0.2 VCC 0.2 VCC
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(4) Power-on Reset (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter Symbol Pin name Condition Value Min. -- -- Power supply shut off time Oscillation stabilizing time tOFF tOSC VCC -- 1 2 x tC x 221 -- -- ms ns Max. 30 Unit Remarks VCC < 0.2 V before turning power supply For repeated operations
Power supply rising time
tR
VCC
ms
tR
VCC
4.5 V 0.2 V tOFF Sudden change in supply voltage during operation may initiate a power-on sequence. To change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid fluctuations in the supply voltage.
5.0 V VCC 3.0 V
RAM data retention A voltage rising rate of 50 mv/ms or less is recommended.
VSS
VCC
tOSC
(Oscillation stabilizing time)
RST
tRSTL
Set RST pin to "L" level when turning on the device, at least tRSTL duration after the supply voltage reaches Vcc is necessary before turning the RST to "H" level.
tRSTL: Reset input time
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(5) Normal Bus Access Read/write Operation (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter CS0 to CS5 delay time Address delay time Data (parity) delay time Symbol tCHCSL tCHCSH tCHAV tCHDV tCLRL tCLRH tCLWL tCLWH tAVDV tRLDV RD D31 to D00 PAR0 to PAR3 Pin name CLK CS0 to CS5 CLK A23 to A00 CLK D31 to D00 PAR0 to PAR3 CLK RD CLK WR0 to WR3 A23 to A00 D31 to D00 PAR0 to PAR3 -- Condition Value Min. -- -- -- -- -- -- -- -- -- -- 10 0 Max. 15 15 15 15 6 6 6 6 3/2 x tCYC - 25 tCYC - 10 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns *1 *2 *1 Remarks
RD delay time WR0 to WR3 delay time Valid address valid data (parity) input time RD valid data (parity) input time
Data (parity) set up RD tDSRH time RD data (parity) hold time tRHDX
*1: When bus timing is delayed by automatic wait insertion or RDY input, add (tCYC x extended cycle number for delay) to this rating. *2: This rating is for a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equation with 1/2, 1/4, 1/8, respectively. * Equation: (2 - n/2) x tCYC - 25
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BA1 tCYC
BA2
CLK
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
tCHCSL
tCHCSH 2.4 V
CS0 to CS5
0.8 V
tCHAV
A23 to A00
2.4 V 0.8 V
2.4 V 0.8 V
tCLRL
tCLRH 2.4 V
RD
0.8 V tRLDV tAVDV
tRHDX
D31 to D00 PAR0 to PAR3
2.4 V 0.8 V
Read
2.4 V 0.8 V tDSRH
tCLWL
WR0 to WR3
0.8 V
2.4 V tCLWH
tCHDV
D31 to D00 PAR0 to PAR3
2.4 V 0.8 V
Write
2.4 V 0.8 V
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(6) Time-sharing Bus Read/Write Operation (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter ALE delay time CS1 delay time Address delay time Data delay time RD delay time WR0, WR1 delay time Symbol tCLLH tCLLL tCHCSL tCHCSH tCHAV tCHDV tCLRL tCLRH tCLWL tCLWH tDSRH tRHDX Pin name Condition CLK ALE CLK CS1 CLK D31 to D16 CLK D31 to D16 CLK RD CLK WR0, WR1 RD D31 to D16 -- -- -- -- -- -- 10 0 6 6 6 6 tCYC - 10 -- -- ns ns ns ns ns ns ns * Value Min. -- -- -- -- -- -- Max. 6 6 15 15 15 15 Unit ns ns ns ns ns ns Remarks
RD valid data input time tRLDV Data set up RD time RD data hold time
* : When bus timing is delayed by automatic wait insertion or RDY input, add (tCYC x extended cycle number for delay) to this rating.
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MA1 tCYC
MA2
BA1
BA2
CLK
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
0.8 V
2.4 V
tCLLH
tCLLL 0.8 V
ALE
2.4 V
tCHCSL
tCHCSH 2.4 V
CS1
0.8 V
tDSRH
Read cycle D31 to D16 (multiplexed bus)
tRLDV 2.4 V 0.8 V tCHAV tRHDX Address 2.4 V 0.8 V 2.4 V 0.8 V Read 2.4 V 0.8 V
RD
0.8 V tCLRL
2.4 V tCLRH
Write cycle D31 to D16 (multiplexed bus)
2.4 V 0.8 V tCHAV
Address tCHDV
2.4 V 0.8 V
Write
2.4 V 0.8 V
WR0, WR1
0.8 V tCLWL
2.4 V tCLWH
A23 to A00 (non-multiplexed bus)
2.4 V 0.8 V tCHAV
2.4 V 0.8 V
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(7) Ready Input Timing (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter ACLK delay time Symbol Pin name Condition tCLAKH tCLAKL CLK ACLK RDY ACLK ACLK RDY -- Value Min. -- -- 10 0 Max. 6 6 -- -- Unit ns ns ns ns Remarks
RDY set up time ACLK tRDYS ACLK RDY hold time tRDYH
tCYC
CLK
2.4 V
0.8 V
2.4 V
0.8 V
tCLAKH
tCLAKL 0.8 V 2.4 V
ACLK
2.4 V
tRDYS
tRDYS 0.8 V 2.4 V tRDYH
RDY When wait(s) is inserted.
0.8 V
2.4 V tRDYH
RDY When no wait is inserted.
2.4 V
0.8 V
2.4 V
0.8 V
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(8) Hold Timing (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter BGRNT delay time Pin floating BGRNT time BGRNT pin valid time Symbol Pin name Condition tCHBGL tCHBGH tXHAL tHAHV CLK BGRNT -- BGRNT Value Min. -- -- tCYC - 10 tCYC - 10 Max. 6 6 tCYC + 10 tCYC + 10 Unit ns ns ns ns Remarks
Note: There is a delay time of more than 1 cycle from BRQ input to BGRNT change.
tCYC
CLK
2.4 V
2.4 V
2.4 V
2.4 V
BRQ
tCHBGL
tCHBGH 2.4 V
BGRNT
tXHAL
0.8 V
tHAHV 2.4 V 0.8 V
Each pin
2.4 V 0.8 V
High impedance
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(9) Normal DRAM Mode Read/Write Cycle (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter RAS delay time CAS delay time ROW address delay time COLUMN address delay time DW delay time Output data (parity) delay time Symbol tCLRAH tCHRAL tCLCASL tCLCASH tCHRAV tCHCAV tCHDWL tCHDWH tCHDV1 Pin name CLK RAS CLK CAS CLK A23 to A00 CLK DW CLK D31 to D00 PAR0 to PAR3 RAS D31 to D00 PAR0 to PAR3 CAS D31 to D00 PAR0 to PAR3 Condition Value Min. -- -- -- -- -- -- -- -- -- -- Max. 6 6 6 6 15 15 15 15 15 5/2 x tCYC - 16 tCYC - 10 -- Unit ns ns ns ns ns ns ns ns ns *1 *2 *1 Remarks
RAS valid data (parity) tRLDV input time CAS valid data (parity) tCLDV input time CAS data (parity) hold tCADH time
-- -- 0
ns ns ns
CAS: CS0L to CS1H pins are for CAS signal outputs. DW: DW0, DW1 and CS0H to CS1H are used for WE outputs. *1: When Q1 cycle or Q4 cycle is extended for "1" cycle, add tCYC time to this rating. *2: This rating is for a gear cycle of x 1. When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute "n" in the following equation with 1/2, 1/4, 1/8, respectively. * Equation: (3 - n/2) x tCYC - 16
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Q1 tCYC
Q2
Q3
Q4
Q5
CLK
2.4 V 0.8 V
2.4 V 0.8 V 0.8 V
2.4 V
RAS
tCLRAH
2.4 V
0.8 V tCHRAL tCLCASH tCLCASH 2.4 V
CAS
0.8 V
tCHRAV
tCHCAV ROW address 2.4 V 0.8 V 2.4 V 0.8 V tRLDV tCLDV tCADH Read 2.4 V 0.8 V COLUMN address 2.4 V 0.8 V
A23 to A00
2.4 V 0.8 V
D31 to D00 PAR0 to PAR3
2.4 V 0.8 V
DW
2.4 V 0.8 V tCHDWL tCHDWH
D31 to D00 PAR0 to PAR3
2.4 V 0.8 V tCHDV1
Write
2.4 V 0.8 V
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(10) Normal DRAM Mode Fast Page Read/Write Cycle (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter RAS delay time CAS delay time COLUMN address delay time DW delay time Output data (parity) delay time Symbol tCLRAH tCLCASL tCLCASH tCHCAV tCHDWH tCHDV1 Pin name CLK, RAS CLK CAS CLK A23 to A00 CLK DW CLK D31 to D00 PAR0 to PAR3 CAS D31 to D00 PAR0 to PAR3 -- Condition Value Min. -- -- -- -- -- -- -- 0 Max. 6 6 6 15 15 15 tCYC - 10 -- Unit ns ns ns ns ns ns ns ns * Remarks
CAS valid data (parity) tCLDV input time CAS data (parity) hold time tCADH
CAS: CS0L to CS1H pins are for CAS signal outputs. DW: DW0, DW1 and CS0H to CS1H are used for WE outputs. * : When Q4 cycle is extended for 1 cycle, add tCYC time to this rating.
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Q5
Q4 2.4 V 0.8 V
Q5 0.8 V
Q4
Q5 2.4 V 0.8 V
CLK
tCLRAH
RAS
2.4 V
tCLCASL
tCLCASH 2.4 V
CAS
0.8 V
tCHCAV
A23 to A00
COLUMN address
2.4 V 0.8 V
COLUMN address
2.4 V COLUMN address 0.8 V
2.4 V 0.8 V
tCLDV
tCADH 2.4 V 0.8 V 2.4 V 0.8 V 2.4 V 0.8 V
D31 to D00 PAR0 to PAR3
2.4 V 0.8 V
Read
2.4 V 0.8 V
2.4 V 0.8 V
Read
Read
tCHDWH
DW
2.4 V
tCHDV1
D31 to D00 PAR0 to PAR3
2.4 V 0.8 V
Write
2.4 V 0.8 V
2.4 V 0.8 V
Write
2.4 V 0.8 V
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(11) CBR Refresh (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter RAS delay time CAS delay time Symbol Pin name Condition tCLRAH tCHRAL tCLCASL tCLCASH CLK RAS -- CLK CAS Value Min. -- -- -- -- Max. 6 6 6 6 Unit ns ns ns ns Remarks
CAS: CS0L to CS1H pins are for CAS signal outputs.
tCYC R1
R2 0.8 V
R3 2.4 V
R4 0.8 V
CLK
2.4 V
0.8 V
RAS
2.4 V tCLRAH
0.8 V tCHRAL
CAS
0.8 V tCLCASL
2.4 V tCLCASH
DW
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(12) Self Refresh (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter RAS delay time CAS delay time Symbol Pin name Condition tCLRAH tCHRAL tCLCASL tCLCASH CLK RAS -- CLK CAS Value Min. -- -- -- -- Max. 6 6 6 6 Unit ns ns ns ns Remarks
CAS: CS0L to CS1H pins are for CAS signal outputs.
tCYC SR1
SR2 2.4 V 0.8 V
SR3 2.4 V
SR3 0.8 V
CLK
2.4 V
tCHRAL
tCLRAH 2.4 V
RAS
0.8 V
CAS
0.8 V tCLCASL
2.4 V tCLCASH
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(13) UART Timing (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter Serial clock cycle time Valid SIN SCLK SCLK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width Valid SIN SCLK SCLK valid SIN hold time Symbol Pin name Condition tSCYC tIVSH tSHIX tSHSL tSLSH tIVSH tSHIX -- -- -- -- -- -- -- -- -- External shift clock mode Internal shift clock mode Value Min. 8 tCYCP -80 100 60 4 tCYCP 4 tCYCP -- 60 60 Max. -- 80 -- -- -- -- 150 -- -- Unit ns ns ns ns ns ns ns ns ns Remarks
SCLK SOUT delay time tSLOV
SCLK SOUT delay time tSLOV
Notes: * This rating is for AC characteristics in CLK synchronous mode. * tCYCP is a cycle time of peripheral system clock.
* Internal shift clock mode
tSCYC
SCLK
0.8 V tSLOV 2.4 V 0.8 V tIVSH
2.4 V 0.8 V
SOUT
tSHIX 2.4 V 0.8 V
SIN
2.4 V 0.8 V
* External shift clock mode
tSLSH tSHSL 2.4 V 0.8 V tSLOV 2.4 V 0.8 V tIVSH tSHIX 2.4 V 0.8 V 0.8 V 2.4 V
SCLK
SOUT
SIN
2.4 V 0.8 V
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(14) I/O Extended Serial Timing (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter Serial clock cycle time Valid SIN SCLK SCLK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width Valid SIN SCLK SCLK valid SIN hold time Symbol Pin name Condition tSCYC tIVSH tSHIX tSHSL tSLSH tIVSH tSHIX -- -- -- -- -- -- -- -- -- External shift clock mode Internal shift clock mode Value Min. 8 tCYCP -- 1 tCYCP 1 tCYCP 230 230 -- 1 tCYCP 2 tCYCP Max. -- 80 -- -- -- -- 2 tCYCP -- -- Unit ns ns ns ns ns ns ns ns ns Max. external frequency is 2 MHz Remarks
SCLK SOUT delay time tSLOV
SCLK SOUT delay time tSLOV
Note: tCYCP is a cycle time of peripheral system clock.
* Internal shift clock mode
tSCYC
SCLK
0.8 V tSLOV 2.4 V 0.8 V tIVSH
2.4 V 0.8 V
SOUT
tSHIX 2.4 V 0.8 V
SIN
2.4 V 0.8 V
* External shift clock mode
tSLSH tSHSL 2.4 V 0.8 V tSLOV 2.4 V 0.8 V tIVSH tSHIX 2.4 V 0.8 V 2.4 V
SCLK
SOUT
SIN
2.4 V 0.8 V
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(15) Timer System Input Timing (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter Input pulse width Symbol Pin name Condition tTIWH tTIWL TI0, TI1 -- Value Min. 2 tCYCP Max. -- Unit ns Remarks
Note: tCYCP is a cycle time of peripheral system clock.
2.4 V
2.4 V 0.8 V 0.8 V
TI0, TI1
tTIWH
tTIWL
(16) Trigger System Input Timing (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter A/D start trigger input time Input capture input trigger Symbol Pin name Condition tATGX tINP ATG IC0 to IC3 -- Value Min. 5 tCYCP 5 tCYCP Max. -- -- Unit ns ns Remarks
Note: tCYCP is a cycle time of peripheral system clock.
tATGX, tINP
ATG IC0 to IC3
0.8 V
0.8 V
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(17) Up/Down Counter Input Timing (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter AIN input "1" pulse width AIN input "0" pulse width BIN input "1" pulse width BIN input "0" pulse width AIN BIN time BIN AIN time AIN BIN time BIN AIN time BIN AIN time AIN BIN time BIN AIN time AIN BIN time ZIN input "1" pulse width ZIN input "0" pulse width Symbol Pin name Condition tAHL tALL tBHL tBLL tAUBU tBUAD tADBD tBDAU tBUAU tAUBD tBDAD tADBU tZHL tZLL ZIN0 ZIN1 AIN0 AIN1 BIN0 BIN1 Value Min. 8 tCYCP 8 tCYCP 8 tCYCP 8 tCYCP 4 tCYCP 4 tCYCP -- 4 tCYCP 4 tCYCP 4 tCYCP 4 tCYCP 4 tCYCP 4 tCYCP 4 tCYCP 4 tCYCP Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks
Note: tCYCP is a cycle time of peripheral system clock.
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tAHL
tALL 2.4 V 0.8 V 0.8 V 2.4 V
AIN
2.4 V
tAUBU
tBUAD 2.4 V
tADBD 2.4 V 0.8 V
tBDAU
BIN
0.8 V
tBHL
tBLL
tBHL
tBLL 2.4 V 0.8 V 0.8 V 2.4 V
BIN
2.4 V
tBUAU
tAUBD 2.4 V
tBDAD 2.4 V 0.8 V
tADBU
AIN
0.8 V
tAHL
tALL
2.4 V
2.4 V
ZIN
tZHL tZLL
0.8 V
0.8 V
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(18) DMA Controller Timing (VCC = +5.0 V10%, VSS = 0.0 V, TA = -10C to +70C) Parameter DREQ input pulse width Symbol Pin name Condition tDRWH DREQ0 DREQ1 DACK0 DACK1 DACK0 DACK1 -- Value Min. 2 tCYC tCYC tCYC Max. -- 3 tCYC 3 tCYC Unit ns ns ns Remarks
DACK "H" output pulse width tDAWH DACK "L" output pulse width tDAWL
tCYC
CLK
2.4 V
2.4 V
tDRWH
DREQ0, DREQ1
2.4 V
2.4 V
tDAWH
DACK0, DACK1 ("H" output)
2.4 V
2.4 V
tDAWL
DACK0, DACK1 ("L" output)
0.8 V
0.8 V
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5. A/D Conversion Block Electrical Characteristics
(AVCC = VCC = +4.5 V to +5.5 V, AVSS = VSS = 0.0 V, TA = -10C to +70C, +4.5 V AVRH - AVRL) Parameter Resolution Total error Linearity error Differentiation linearity error Zero transition voltage Full-scale transition voltage Conversion time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Conversion variance between channels Symbol -- -- -- -- VOT VFST -- IAIN VAIN -- -- IA IAH IR IRH -- Pin name -- -- -- -- AN0 to AN7 -- AN0 to AN7 AN0 to AN7 AVRH AVRL AVCC AVRH AN0 to AN7 Value Min. -- -- -- -- Typ. 10 -- -- -- Max. 10 3.0 2.0 1.5 Unit BIT LSB LSB LSB
AVRL - 1.5 AVRL + 0.5 AVRL + 2.5 LSB 5.6 *1 -- AVRL AVRL AVSS -- -- -- -- -- -- 0.1 -- -- -- 4 -- 200 -- -- -- 10 AVRH AVCC AVRH -- 5*
2
AN0 to AN7 AVRH - 4.5 AVRH - 1.5 AVRH + 0.5 LSB s A V V V mA A A
2
-- 170 * 4
A LSB
*1: VCC = 5.0 V 10%, machine clock of 25 MHz *2: Current value for A/D converters not in operation, CPU stop mode (VCC = AVCC = AVRH = 5.0 V) Notes: * As the absolute value of |AVRH-AVRL| decreases, relative error increases. * Output impedance of external circuit of analog input under following conditions; Output impedance of external circuit < 7 k approx. If output impedance of external circuit is too high, analog voltage sampling time may be too short for accurate sampling (sampling time is 5.6 s for a machine clock of 25 MHz).
* Analog input circuit model plan
Sample & hold circuit Analog input RON1 RON2 RON3 RON4 C1 RON1 = 1.5 k approx. RON2 = 0.5 k approx. RON3 = 0.5 k approx. RON4 = 0.5 k approx. C0 = 60 pF approx. C1 = 4 pF approx. Note: Listed values are for reference purposes only. C0 Comparator
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6. Definitions of A/D Converter Descriptions
* Resolution The smallest change in analog voltage detected by A/D converter. * Linearity error A deviation of actual conversion characteristic from a line connecting the zero-traction point (between "00 0000 0000" "00 0000 00001") to the full-scale transition point (between "11 1111 1110" "11 1111 1111"). * Differential linearity error A deviation of a step voltage for changing the LSB of output code from ideal input voltage. * Total error A difference between actual value and theoretical value. The overall error includes zero-transition error, fullscale transition error and linearity error.
Total error 3FF 1.5LSB' 3FE Actual conversion characteristic 3FD Digital output {1LSB'x(N-1)+0.5LSB'}
004 003 002 001 0.5 LSB' AVRL Analog input AVRH VNT (measured value) Actual conversion characteristic Ideal characteristic
1LSB' (Ideal value) =
AVRH - AVRL 1024
[V]
Total error of = digital output N
VNT - {1 LSB' x (N - 1) + 0.5 LSB'} 1 LSB'
VOT'
(Ideal value) = AVRL + 0.5 LSB' [V] VNT: A voltage for causing transition of digital output from (N-1) to N
VFST' (Ideal value) = AVRL + 1.5 LSB' [V]
(Continued)
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(Continued)
Linearity error 3FF 3FE {1 LSB x (N - 1) + VOT} 3FD Digital output VFST (measured value) 004 003 002 Ideal characteristic 001 VOT (measured value) AVRL Analog input AVRH AVRL N-2 VNT (measured value) Actual conversion characteristic Digital output N
Differential linearity error
Actual conversion characteristic N+1 Actual characteristic
Ideal characteristic
N-1 V(N+1)T VNT (measured value) (measured value) Actual conversion characteristic AVRH Analog input
Linearity error of digital output N =
VNT - {1 LSB' x (N - 1) + VOT} 1 LSB [LSB]
Differential linearity error of digital output N =
V(N+1)T - VNT 1 LSB -1 [LSB]
1 LSB =
VFST - VOT 1022
[V]
VOT: A voltage for causing transition of digital output from (000)H to (001)H VFST: A voltage for causing transition of digital output from (3FE)H to (3FF)H
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s OUTPUT VS LOAD CAPACITANCE CHARACTERISTIC
t (ns) 3.5 Output vs load capacitance characteristic
3
2.5
2
1.5
1
0.5
0 80
85
90
95
100
105
110
115
120 C (pF)
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s INSTRUCTIONS
1. How to Read Instruction Set Summary
Mnemonic ADD * ADD Rj, Ri #s5, Ri , , (2) Type A C , , (3) OP A6 A4 , , (4) ~ 1 1 , , (5) NZVC CCCC CCCC , , (6) Operation Ri + Rj Ri Ri + s5 Ri , , (7) Remarks
(1)
(1) Names of instructions. Instructions marked with * are not included in CPU specifications. These are extended instruction codes added/extended at assembly language levels. (2) Addressing modes specified as operands are listed in symbols. Refer to "2. Addressing mode symbols" for further information. (3) Instruction types. (4) Hexa-decimal expressions of instructions. (5) Number of machine cycles needed for execution. a: Memory access cycle. May be extended by Ready function. b: b: Memory access cycle. May be extended by Ready function. If an object register in a LD operation is referenced by an immediately following instruction, the interlock function is activated and number of cycles needed for execution increases. c: If an immediately following instruction operates to an object of R15, SSP or USP in read/write mode or if the instruction belongs to instruction format A group, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. d: If an immediately following instruction refers to MDH/MDL, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. For a, b, c and d, minimum execution cycle is 1. (6) Change in flag sign. * Flag meanings N : Negative flag Z : Zero flag V : Over flag C : Carry flag * Flag change C : Change - : No change 0 : Clear 1 : Set (7) Operation carried out by instruction.
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2. Addressing Mode Symbols
: Register direct (R0 to R15, AC, FP, SP) : Register direct (R0 to R15, AC, FP, SP) : Register direct (R13, AC) : Register direct (Program status register) : Register direct (TBR, RP, SSP, USP, MDH, MDL) : Register direct (CR0 to CR15) : Register direct (CR0 to CR15) : Unsigned 8-bit immediate (-128 to 255) Note: -128 to -1 are interpreted as 128 to 255 #i20 : Unsigned 20-bit immediate (-0X80000 to 0XFFFFF) Note: -0X7FFFF to -1 are interpreted as 0X7FFFF to 0XFFFFF #i32 : Unsigned 32-bit immediate (-0X80000000 to 0XFFFFFFFF) Note: -0X80000000 to -1 are interpreted as 0X80000000 to 0XFFFFFFFF #s5 : Signed 5-bit immediate (-16 to 15) #s10 : Signed 10-bit immediate (-512 to 508, multiple of 4 only) #u4 : Unsigned 4-bit immediate (0 to 15) #u5 : Unsigned 5-bit immediate (0 to 31) #u8 : Unsigned 8-bit immediate (0 to 255) #u10 : Unsigned 10-bit immediate (0 to 1020, multiple of 4 only) @dir8 : Unsigned 8-bit direct address (0 to 0XFF) @dir9 : Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only) @dir10 : Unsigned 10-bit direct address (0 to 0X3FC, multiple of 4 only) label9 : Signed 9-bit branch address (-0X100 to 0XFC, multiple of 2 only) label12 : Signed 12-bit branch address (-0X800 to 0X7FC, multiple of 2 only) label20 : Signed 20-bit branch address (-0X80000 to 0X7FFFF) label32 : Signed 32-bit branch address (-0X80000000 to 0X7FFFFFFF) @Ri : Register indirect (R0 to R15, AC, FP, SP) @Rj : Register indirect (R0 to F15, AC, FP, SP) @(R13, Rj) : Register relative indirect (Rj: R0 to R15, AC, FP, SP) @(R14, disp10) : Register relative indirect (disp10: -0X200 to 0X1FC, multiple of 4 only) @(R14, disp9) : Register relative indirect (disp9: -0X100 to 0XFE, multiple of 2 only) @(R14, disp8) : Register relative indirect (disp8: -0X80 to 0X7F) @(R15, udisp6) : Register relative (udisp6: 0 to 60, multiple of 4 only) @Ri+ : Register indirect with post-increment (R0 to R15, AC, FP, SP) @R13+ : Register indirect with post-increment (R13, AC) @SP+ : Stack pop @-SP : Stack push (reglist) : Register list Ri Rj R13 Ps Rs CRi CRj #i8
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3. Instruction Types
MSB 16 bit OP 8 Rj 4 Ri 4 LSB
Type A
Type B
OP 4
i8/o8 8
Ri 4
Type C
OP 8
u4/m4 4
Ri 4
ADD, ADDN, CMP, LSL, LSR and ASR instructions only Type *C' OP 7 s5/u5 5 Ri 4
Type D
OP 8
u8/rel8/dir/reglist 8
Type E
OP 8
SUB-OP 4
Ri 4
Type F
OP 5
rel11 11
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4. Detailed Description of Instructions
* Add/subtract operation instructions Mnemonic ADD * ADD ADD ADD2 ADDC ADDN * ADDN ADDN ADDN2 SUB SUBC SUBN Rj, Ri #s5, Ri #u4, Ri #u4, Ri Rj, Ri Rj, Ri #s5, Ri #u4, Ri #u4, Ri Rj, Ri Rj, Ri Rj, Ri Type A C' C C A A C' C C A A A OP A6 A4 A4 A5 A7 A2 A0 A0 A1 AC AD AE Cycle N Z V C 1 1 1 1 1 1 1 1 1 1 1 1 Operation Remarks MSB is interpreted as a sign in assembly language Zero-extension Sign-extension Add operation with sign MSB is interpreted as a sign in assembly language Zero-extension Sign-extension
C C C C Ri + Rj Ri C C C C Ri + s5 Ri C C C C Ri + extu (i4) Ri C C C C Ri + extu (i4) Ri C C C C Ri + Rj + c Ri - - - - Ri + Rj Ri - - - - Ri + s5 Ri - - - - Ri + extu (i4) Ri - - - - Ri + extu (i4) Ri C C C C Ri - Rj Ri C C C C Ri - Rj - c Ri - - - - Ri - Rj Ri
Subtract operation with carry
* Compare operation instructions Mnemonic CMP * CMP CMP CMP2 Rj, Ri #s5, Ri #u4, Ri #u4, Ri Type A C' C C OP AA A8 A8 A9 Cycle N Z V C 1 1 1 1 Operation Remarks MSB is interpreted as a sign in assembly laMnguage Zero-extension Sign-extension
C C C C Ri - Rj C C C C Ri - s5 C C C C Ri + extu (i4) C C C C Ri + extu (i4)
* Logical operation instructions Mnemonic AND AND ANDH ANDB OR OR ORH ORB EOR EOR EORH EORB Rj, Ri Rj, @Ri Rj, @Ri Rj, @Ri Rj, Ri Rj, @Ri Rj, @Ri Rj, @Ri Rj, Ri Rj, @Ri Rj, @Ri Rj, @Ri Type A A A A A A A A A A A A OP 82 84 85 86 92 94 95 96 9A 9C 9D 9E Cycle N Z V C 1 1+2a 1+2a 1+2a 1 1+2a 1+2a 1+2a 1 1+2a 1+2a 1+2a CC CC CC CC CC CC CC CC CC CC CC CC - - - - - - - - - - - - - - - - - - - - - - - - Ri & (Ri) & (Ri) & (Ri) & Ri (Ri) (Ri) (Ri) | | | | Operation = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj = Rj Remarks Word Word Half word Byte Word Word Half word Byte Word Word Half word Byte
Ri ^ (Ri) ^ (Ri) ^ (Ri) ^
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* Bit manipulation instructions Mnemonic BANDL BANDH * BAND BORL BORH * BOR BEORL BEORH * BEOR BTSTL BTSTH #u4, @Ri #u4, @Ri #u8, @Ri *1 #u4, @Ri #u4, @Ri #u8, @Ri *2 #u4, @Ri #u4, @Ri #u8, @Ri *3 #u4, @Ri #u4, @Ri C C 88 89 2+a 2+a 0 C - - (Ri) & u4 C C - - (Ri) & (u4 < < 4) Test lower 4 bits Test upper 4 bits C C 98 99 1+2a 1+2a - - - - (Ri) ^ = u4 - - - - (Ri) ^ = (u4 < < 4) - - - - (Ri) ^ = u8 Manipulate lower 4 bits Manipulate upper 4 bits C C 90 91 1+2a 1+2a - - - - (Ri) | = u4 - - - - (Ri) | = (u4 < < 4) - - - - (Ri) | = u8 Manipulate lower 4 bits Manipulate upper 4 bits Type C C OP 80 81 Cycle N Z V C 1+2a 1+2a Operation Remarks
- - - - (Ri) & = (0xF0 + u4) Manipulate lower 4 bits - - - - (Ri) & = ((u4 < < 4) Manipulate upper 4 bits + 0x0F) (Ri) & = u8
*1: Assembler generates BANDL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates BANDH if "u8&0xF0" leaves an active bit. Depending on the value in the "u8" format, both BANDL and BANDH may be generated. *2: Assembler generates BORL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates BORH if "u8&0xF0" leaves an active bit. *3: Assembler generates BEORL if result of logical operation "u8&0x0F" leaves an active (set) bit and generates BEORH if "u8&0xF0" leaves an active bit. * Add/subtract operation instructions Mnemonic MUL MULU MULH MULUH DIVOS DIVOU DIV1 DIV2 DIV3 DIV4S * DIV * DIVU Rj, Ri Rj, Ri Rj, Ri Rj, Ri Ri Ri Ri Ri Ri *1 Ri *2 *1: DIVOS, DIV1 x 32, DIV2, DIV3 and DIV4S are generated. A total instruction code length of 72 bytes. *2: DIVOU and DIV1 x 32 are generated. A total instruction code length of 66 bytes. 33 Type A A A A E E E E E E OP AF AB BF BB 97-4 97-5 97-6 97-7 9F-6 9F-7 Cycle N Z V C 5 5 3 3 1 1 d 1 1 1 36 CCC CCC CC - CC - - - - - - - - - - C C - - C - - - - - - - - - - - Operation Ri * Rj MDH, MDL Ri * Rj MDH, MDL Ri * Rj MDL Ri * Rj MDL Remarks 32-bit*32-bit = 64-bit Unsigned 16-bit*16-bit = 32-bit Unsigned Step calculation 32-bit/32-bit = 32-bit
- - C C - - C MDL/Ri MDL, MDL%Ri MDH
- C - C MDL/Ri MDL, MDL%Ri MDH
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* Shift instructions Mnemonic LSL * LSL LSL * LSL2 LSR * LSR LSR * LSR2 ASR * ASR ASR * ASR2 Rj, Ri #u5, Ri (u5: 0 ~ 31) #u4, Ri #u4, Ri Rj, Ri #u5, Ri (u5: 0 ~ 31) #u4, Ri #u4, Ri Rj, Ri #u5, Ri (u5: 0 ~ 31) #u4, Ri #u4, Ri Type A C' C C A C' C C A C' C C OP B6 B4 B4 B5 B2 B0 B0 B1 BA B8 B8 B9 Cycle N Z V C 1 1 1 1 1 1 1 1 1 1 1 1 CC CC CC CC CC CC CC CC CC CC CC CC - - - - - - - - - - - - C C C C C C C C C C C C Operation Ri < < Rj Ri Ri < < u5 Ri Ri < < u4 Ri Ri < < (u4 + 16) Ri Ri > > Rj Ri Ri > > u5 Ri Ri > > u4 Ri Ri > > (u4 + 16) Ri Ri > > Rj Ri Ri > > u5 Ri Ri > > u4 Ri Ri > > (u4 + 16) Ri Remarks Logical shift
Logical shift
Logical shift
* Immediate value set/16-bit/32-bit immediate value transfer instruction Mnemonic LDI:32 LDI:20 LDI:8 * LDI #i32, Ri #i20, Ri #i8, Ri # {i8 | i20 | i32}, Ri Type E C B OP 9F-8 9B C0 Cycle N Z V C 3 2 1 Operation Remarks Upper 12-bit is zero-extended Upper 24-bit is zero-extended
- - - - i32 Ri - - - - i20 Ri - - - - i8 Ri {i8 | i20 | i32} Ri
* : If an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection. If an immediate value contains relative value or external reference, assembler selects i32. * Memory load instructions Mnemonic LD LD LD LD LD LD LD LDUH LDUH LDUH LDUB LDUB LDUB @Rj, Ri @(R13, Rj), Ri @(R14, disp10), Ri @(R15, udisp6), Ri @R15 +, Ri @R15 +, Rs @R15 +, PS @Rj, Ri @(R13, Rj), Ri @(R14, disp9), Ri @Rj, Ri @(R13, Rj), Ri @(R14, disp8), Ri Type A A B C E E E A A B A A B OP 04 00 20 03 07-0 07-8 07-9 05 01 40 06 02 60 Cycle N Z V C b ---- b ---- b ---- b ---- b ---- b ---- 1+a+b C C C C b b b b b b Operation (Rj) Ri (R13 + Rj) Ri (R14 + disp10) Ri (R15 + udisp6) Ri (R15) Ri, R15 + = 4 (R15) Rs, R15 + = 4 (R15) PS, R15 + = 4 Remarks
Rs: Special register * Zero-extension Zero-extension Zero-extension Zero-extension Zero-extension Zero-extension
- - - - (Rj) Ri - - - - (R13 + Rj) Ri - - - - (R14 + disp9) Ri - - - - (Rj) Ri - - - - (R13 + Rj) Ri - - - - (R14 + disp8) Ri
* : Assembler calculates and set the result in the field of o8, o4 format given by hardware specification. disp10/4 o8, disp9/2 o8, disp8 o8, disp10, disp9, disp8 are signed udisp6/4 o4, udisp6 are unsigned.
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MB91103 Series
* Memory store instructions Mnemonic ST ST ST ST ST ST ST STH STH STH STB STB STB Ri, @Rj Ri, @(R13, Rj) Ri, @(R14, disp10) Ri, @(R15, udisp6) Ri, @-R15 Rs, @-R15 PS, @-R15 Ri, @Rj Ri, @(R13, Rj) Ri, @(R14, disp9) Ri, @Rj Ri, @(R13, Rj) Ri, @(R14, disp8) Type A A B C E E E A A B A A B OP 14 10 30 13 17-0 17-8 17-9 15 11 50 16 12 70 Cycle N Z V C a a a a a a a a a a a a a - - - - - - - - - - - - - - - - - - - - - - - - - - - - Operation Ri (Rj) Ri (R13 + Rj) Ri (R14 + disp10) Ri (R15 + usidp6) R15 - = 4, Ri (R15) R15 - = 4, Rs (R15) R15 - = 4, PS (R15) Word Word Word Rs: Special register * Half word Half word Half word Byte Byte Byte Remarks
- - - - Ri (Rj) - - - - Ri (R13 + Rj) - - - - Ri (R14 + disp9) - - - - Ri (Rj) - - - - Ri (R13 + Rj) - - - - Ri (R14 + disp8)
* : Assembler calculates and set the result in the field of o8, o4 format given by hardware specification. disp10/4 o8, disp9/2 o8, disp8 o8, disp10, disp9, disp8 are signed udisp6/4 o4, udisp6 are unsigned. * Transfer instructions between registers Mnemonic MOV MOV MOV MOV MOV Rj, Ri Rs, Ri Ri, Rs PS, Ri Ri, PS Type A A A E E OP 8B B7 B3 17-1 07-1 Cycle N Z V C 1 1 1 1 c Operation Remarks Transfer between general-purpose registers Rs: Special register Rs: Special register *
- - - - Rj Ri ---- ---- ---- CCCC Rs Ri Ri Rs PS Ri Ri PS
* : Special registers Rs: TBR, RP USP, SSP, MDH, MDL
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* Normal branch (non-delay) instructions Mnemonic JMP CALL CALL RET INT #u8 @Ri label12 @Ri Type E F E E D OP 97-0 D0 97-1 97-2 1F Cycle N Z V C 2 2 2 2 3+3a Operation Remarks
- - - - Ri PC - - - - PC + 2 RP, PC + 2 + (label12 - PC - 2) PC - - - - PC + 2 RP, Ri PC - - - - RP PC Return - - - - SSP - = 4, PS (SSP), SSP - = 4, PC + 2 (SSP), 0 I flag, 0 S flag, (TBR + 0x3FC - u8 x 4) PC - - - - SSP - = 4, PS (SSP), For emulator SSP - = 4, PC + 2 (SSP), 0 S flag, (TBR + 0x3D8) PC C C C C (R15) PC, R15 - = 4, (R15) PS, R15 - = 4 - - - - PC + 2 + (label9 - PC - 2) PC - - - - Non-branch - - - - if (Z = = 1) then PC + 2 + (label9 - PC - 2) PC - - - - PCx/Z = = 0 - - - - PCs/C = = 1 - - - - PCs/C = = 0 - - - - PCs/N = = 1 - - - - PCs/N = = 0 - - - - PCs/V = = 1 - - - - PCs/V = = 0 - - - - PCs/V xor N = = 1 - - - - PCs/V xor N = = 0 - - - - PCs/(V xor N) or Z = = 1 - - - - PCs/(V xor N) or Z = = 0 - - - - PCs/C or Z = = 1 - - - - PCs/C or Z = = 0
INTE
E
9F-3
3+3a
RETI BRA BNO BEQ BNE BC BNC BN BP BV BNV BLT BGE BLE BGT BLS BHI label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9
E D D D D D D D D D D D D D D D D
97-3 E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF
2+2a 2 1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1
Notes: * Number of cycles "2/1" indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch. * Assembler calculates and set the result in the field of rel11 and rel8 format given by hardware specification. (label12 - PC - 2)/2 rel11, (label9 - PC - 2)/2 rel8, label12, label9 are signed. * RETI must be operated while S flag = 0.
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* Branch instructions with delays Mnemonic JMP:D CALL:D CALL:D RET:D BRA:D BNO:D BEQ:D BNE:D BC:D BNC:D BN:D BP:D BV:D BNV:D BLT:D BGE:D BLE:D BGT:D BLS:D BHI:D label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 @Ri label12 @Ri Type E F E E D D D D D D D D D D D D D D D D OP 9F-0 D8 9F-1 9F-2 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Cycle N Z V C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Operation Remarks
- - - - Ri PC - - - - PC + 4 RP, PC + 2 + (label12 - PC - 2) PC - - - - PC + 4 RP, Ri PC - - - - RP PC - - - - PC + 2 + (label9 - PC - 2) PC - - - - Non-branch - - - - if (Z = = 1) then PC + 2 + (label9 - PC - 2) PC - - - - PCs/Z = = 0 - - - - PCs/C = = 1 - - - - PCs/C = = 0 - - - - PCs/N = = 1 - - - - PCs/N = = 0 - - - - PCs/V = = 1 - - - - PCs/V = = 0 - - - - PCs/V xor N = = 1 - - - - PCs/V xor N = = 0 - - - - PCs/(V xor N) or Z = = 1 - - - - PCs/(V xor N) or Z = = 0 - - - - PCs/C or Z = = 1 - - - - PCs/C or Z = = 0 Return
Notes: * Assembler calculates and set the result in the field of rel11 and rel8 format given by hardware specification. (label12 - PC - 2)/2 rel11, (label9 - PC - 2)/2 rel8, label12, label9 are signed. * Delayed branch operation always executes next instruction (delay slot) before making a branch. * Instructions allowed to be stored in the delay slot are all 1-cycle, a, b, c and d-cycle instructions. Multiplecycle instructions are no to allowed on the delay slot.
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* Others Mnemonic NOP ANDCCR #u8 ORCCR #u8 STILM ADDSP EXTSB EXTUB EXTSH EXTUH LDM0 LDM1 * LDM #u8 #s10 *1 Ri Ri Ri Ri (reglist) (reglist) (reglist) *2 STM0 STM1 * STM2 (reglist) (reglist) (reglist) *3 ENTER #u10 *4 LEAVE XCHB @Rj, Ri E A 9F-9 8A b 2a - - - - R14 + 4 R15, (R15 - 4) R14 - - - - Rj TEMP (Rj) Ri TEMP (Rj) Exit processing of function For SEMAFO management Byte data D 0F 1+a - - - - R14 (R15 - 4), R15 - 4 R14, R15 - u10 R15 Entrance processing of function D D 8E 8F - - - - R15 decrement, reglist (R15) - - - - R15 decrement, reglist (R15) - - - - R15 decrement, reglist (R15) Store-multi R0 to R7 Store-multi R8 to R15 Store-multi R0 to R15 E E E E D D 97-8 97-9 97-A 97-B 8C 8D 1 1 1 1 - - - - - - - - - - - - - - - - Sign extension 8 32-bit Zero extension 8 32-bit Sign extension 16 32 bit Zero extension 16 32-bit Load-multi R0 to R7 Load-multi R8 to R15 Load-multi R0 to R15 Type E D D D D OP 9F-A 83 93 87 A3 Cycle N Z V C 1 c c 1 1 Operation Remarks
- - - - No changes C C C C CCR and u8 CCR C C C C CCR or u8 CCR - - - - i8 ILM - - - - R15 + = s10 Set ILM immediate value ADD SP instruction
- - - - (R15) reglist, R15 increment - - - - (R15) reglist, R15 increment - - - - (R15) reglist, R15 increment
*1: For s10 format, assembler calculates s10/4 and convert to s8 format. s10 is signed. *2: If either of R0 to R7 is specified in reglist, assembler generates LDM0. If either of R8 to R15 is specified, assembler generates LDM1. Both LDM0 and LDM1 may be generated. *3: If either of R0 to R7 is specified in reglist, assembler generates STM0. If either of R8 to R15 is specified, assembler generates STM1. Both STM0 and STM1 may be generated. *4: For u10 format, assembler calculates u10/4 and convert to s8 format. u10 is unsigned. Notes: * Number of cycles needed for execution of LDM0 (reglist) and LDM1 (reglist) is given by the following calculation; a*(n - 1) + b + 1 where n is number of registers specified. * Number of cycles needed for execution of STM0 (reglist) and STM1 (reglist) is given by the following calculation; a*n + 1 where n is number of registers specified. 107
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* 20-bit normal branch macro instructions Mnemonic * CALL20 * BRA20 * BEQ20 * BNE20 * BC20 * BNC20 * BN20 * BP20 * BV20 * BNV20 * BLT20 * BGE20 * BLE20 * BGT20 * BLS20 * BHI20 label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri Operation Next instruction address RP, label20 PC label20 PC if (Z = = 1) then label20 PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Remarks Ri: Temporary register *1 Ri: Temporary register *2 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3
*1: CALL20 (1) If label20-PC-2 is between -0x800 and +0x7fe, instruction is generated as follows; CALL label12 (2) If label20-PC-2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri CALL @Ri *2: BRA20 (1) If label20-PC-2 is between -0x100 and +0xfe, instruction is generated as follows; BRA label9 (2) If label20-PC-2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri JMP @Ri *3: Bcc20 (BEQ20 to BHI20) (1) If label20-PC-2 is between -0x100 and +0xfe, instruction is generated as follows; Bcc label9 (2) If label20-PC-2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:20 #label20, Ri JMP @Ri false:
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* 20-bit delayed branch macro instructions Mnemonic * CALL20:D label20, Ri * BRA20:D * BEQ20:D * BNE20:D * BC20:D * BNC20:D * BN20:D * BP20:D * BV20:D * BNV20:D * BLT20:D * BGE20:D * BLE20:D * BGT20:D * BLS20:D * BHI20:D label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri label20, Ri Operation Next instruction address + 2 RP, label20 PC label20 PC if (Z = = 1) then label20 PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Remarks Ri: Temporary register *1 Ri: Temporary register *2 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3
*1: CALL20:D (1) If label20-PC-2 is between -0x800 and +0x7fe, instruction is generated as follows; CALL:D label12 (2) If label20-PC-2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri CALL:D @Ri *2: BRA20:D (1) If label20-PC-2 is between -0x100 and +0xfe, instruction is generated as follows; BRA:D label9 (2) If label20-PC-2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:20 #label20, Ri JMP:D @Ri *3: Bcc20:D (BEQ20:D to BHI20:D) (1) If label20-PC-2 is between -0x100 and +0xfe, instruction is generated as follows; Bcc:D label9 (2) If label20-PC-2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:20 #label20, Ri JMP:D @Ri false:
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* 32-bit normal macro branch instructions Mnemonic * CALL32 * BRA32 * BEQ32 * BNE32 * BC32 * BNC32 * BN32 * BP32 * BV32 * BNV32 * BLT32 * BGE32 * BLE32 * BGT32 * BLS32 * BHI32 label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri Operation Next instruction address RP, label32 PC label32 PC if (Z = = 1) then label32 PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Remarks Ri: Temporary register *1 Ri: Temporary register *2 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3
*1: CALL32 (1) If label32-PC-2 is between -0x800 and +0x7fe, instruction is generated as follows; CALL label12 (2) If label32-PC-2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri CALL @Ri *2: BRA32 (1) If label32-PC-2 is between -0x100 and +0xfe, instruction is generated as follows; BRA label9 (2) If label32-PC-2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri JMP @Ri *3: Bcc32 (BEQ32 to BHI32) (1) If label32-PC-2 is between -0x100 and +0xfe, instruction is generated as follows; Bcc label9 (2) If label32-PC-2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:32 #label32, Ri JMP @Ri false:
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* 32-bit delayed macro branch instructions Mnemonic * CALL32:D label32, Ri * BRA32:D * BEQ32:D * BNE32:D * BC32:D * BNC32:D * BN32:D * BP32:D * BV32:D * BNV32:D * BLT32:D * BGE32:D * BLE32:D * BGT32:D * BLS32:D * BHI32:D label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri label32, Ri Operation Next instruction address + 2 RP, label32 PC label32 PC if (Z = = 1) then label32 PC ifs/Z = = 0 ifs/C = = 1 ifs/C = = 0 ifs/N = = 1 ifs/N = = 0 ifs/V = = 1 ifs/V = = 0 ifs/V xor N = = 1 ifs/V xor N = = 0 ifs/(V xor N) or Z = = 1 ifs/(V xor N) or Z = = 0 ifs/C or Z = = 1 ifs/C or Z = = 0 Remarks Ri: Temporary register *1 Ri: Temporary register *2 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3 Ri: Temporary register *3
*1: CALL32:D (1) If label32-PC-2 is between -0x800 and +0x7fe, instruction is generated as follows; CALL:D label12 (2) If label32-PC-2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri CALL:D @Ri *2: BRA32:D (1) If label32-PC-2 is between -0x100 and +0xfe, instruction is generated as follows; BRA:D label9 (2) If label32-PC-2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; LDI:32 #label32, Ri JMP:D @Ri *3: Bcc32:D (BEQ32:D to BHI32:D) (1) If label32-PC-2 is between -0x100 and +0xfe, instruction is generated as follows; Bcc:D label9 (2) If label32-PC-2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:32 #label32, Ri JMP:D @Ri false:
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* Direct addressing instructions Mnemonic DMOV DMOV DMOV DMOV DMOV DMOV DMOVH DMOVH DMOVH DMOVH DMOVB DMOVB DMOVB DMOVB @dir10, R13, @dir10, @R13+, @dir10, @R15+, @dir9, R13, @dir9, @R13+, @dir8, R13, @dir8, @R13+, R13 @dir10 @R13+ @dir10 @-R15 @dir10 R13 @dir9 @R13+ @dir9 R13 @dir8 @R13+ @dir8 Type D D D D D D D D D D D D D D OP 08 18 0C 1C 0B 1B 09 19 0D 1D 0A 1A 0E 1E Cycle N Z V C b a 2a 2a 2a 2a b a 2a 2a b a 2a 2a - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Operation (dir10) R13 R13 (dir10) (dir10) (R13), R13 + = 4 (R13) (dir10), R13 + = 4 R15 - = 4, (R15) (dir10) (R15) (dir10), R15 + = 4 (dir9) R13 R13 (dir9) (dir9) (R13), R13 + = 2 (R13) (dir9), R13 + = 2 (dir8) R13 R13 (dir8) (dir8) (R13), R13 + + (R13) (dir8), R13 + + Word Word Word Word Word Word Half word Half word Half word Half word Byte Byte Byte Byte Remarks
Note: Assembler calculates as follows and set the result value to dir8, dir9 and dir10 fields. dir8 dir, dir9/2 dir, dir10/4 dir, dir8, dir9, dir10 are unsigned. * Resource instructions Mnemonic LDRES STRES @Ri+, #u4, #u4 @Ri+ Type C C OP BC BD Cycle N Z V C a a Operation Remarks u4: Channel number u4: Channel number
- - - - (Ri) u4 resource Ri + = 4 - - - - u4 resource (Ri) Ri + = 4
* Co-processor control instructions {CRi | CRj}: = CR0 | CR1 | CR2 | CR3 | CR4 | CR5 | CR6 | CR7 | CR8 | CR9 | CR10 | CR11 | CR12 | CR13 | CR14 | CR15 u4: Specify channel u8: Specify command Mnemonic COPOP COPLD COPST COPSV #u4, #u8, CRj, CRi #u4, #u8, Rj, CRi #u4, #u8, CRj, Ri #u4, #u8, CRj, Ri Type E E E E OP 9F-C 9F-D 9F-E 9F-F Cycle N Z V C 2+a 1+2a 1+2a 1+2a - - - - - - - - - - - - - - - - Operation Calculation Rj CRi CRj Ri CRj Ri Remarks
No error traps
Note: These instructions are not valid because this model does not have a co-processor.
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s ORDERING INFORMATION
Part number MB91103 Package 160-pin Plastic QFP FPT-160P-M03 Remarks
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s PACKAGE DIMENSIONS
160-pin Plastic QFP (FPT-160P-M03)
32.000.40(1.260.016)SQ 28.000.20(1.102.008)SQ
120 121 81 80
3.85(.152)MAX
(Mounting height)
0(0)MIN (STAND OFF)
25.35 (.998) REF
30.400.40 (1.197.016)
Details of "A" part 0.25(.010) 0.20(.008) 0.18(.007)MAX
INDEX
160 41
0.53(.021)MAX "A"
40
Details of "B" part
LEAD No.
1
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
M
0.150.05 (.006.002)
0
10
0.800.20(.031.008) 0.10(.004) "B"
C
1994 FUJITSU LIMITED F160004S-3C-2
Dimensions in mm (inches)
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FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9707 (c) FUJITSU LIMITED Printed in Japan
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